UART Simulation Results

Tuesday April 29 2025 17:07:08 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.880s	836.252us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.460s	13.289us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.650s	37.745us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.990s	422.645us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.620s	94.114us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.770s	30.523us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.650s	37.745us	1	1	100.00
		uart_csr_aliasing	1.620s	94.114us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.390m	90.823ms	1	1	100.00
V2	parity	uart_smoke	1.880s	836.252us	1	1	100.00
		uart_tx_rx	1.390m	90.823ms	1	1	100.00
V2	parity_error	uart_intr	50.750s	93.352ms	1	1	100.00
		uart_rx_parity_err	10.210s	33.587ms	1	1	100.00
V2	watermark	uart_tx_rx	1.390m	90.823ms	1	1	100.00
		uart_intr	50.750s	93.352ms	1	1	100.00
V2	fifo_full	uart_fifo_full	35.420s	141.733ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	2.521m	137.778ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.343m	63.243ms	1	1	100.00
V2	rx_frame_err	uart_intr	50.750s	93.352ms	1	1	100.00
V2	rx_break_err	uart_intr	50.750s	93.352ms	1	1	100.00
V2	rx_timeout	uart_intr	50.750s	93.352ms	1	1	100.00
V2	perf	uart_perf	1.823m	10.231ms	1	1	100.00
V2	sys_loopback	uart_loopback	4.100s	2.201ms	1	1	100.00
V2	line_loopback	uart_loopback	4.100s	2.201ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	9.890s	19.495ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.920s	40.688ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.430s	1.480ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	36.220s	6.093ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.620m	45.385ms	1	1	100.00
V2	stress_all	uart_stress_all	3.406m	441.468ms	1	1	100.00
V2	alert_test	uart_alert_test	1.500s	152.703us	1	1	100.00
V2	intr_test	uart_intr_test	1.610s	34.733us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.980s	141.824us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.980s	141.824us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.460s	13.289us	1	1	100.00
		uart_csr_rw	1.650s	37.745us	1	1	100.00
		uart_csr_aliasing	1.620s	94.114us	1	1	100.00
		uart_same_csr_outstanding	1.680s	17.141us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.460s	13.289us	1	1	100.00
		uart_csr_rw	1.650s	37.745us	1	1	100.00
		uart_csr_aliasing	1.620s	94.114us	1	1	100.00
		uart_same_csr_outstanding	1.680s	17.141us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.810s	64.446us	1	1	100.00
		uart_tl_intg_err	1.970s	67.805us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.970s	67.805us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	13.120s	1.266ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00