CHIP Simulation Results

Tuesday April 29 2025 17:07:08 UTC

GitHub Revision: `e07399c`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.083m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.083m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.227m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.208m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.076m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.198m	5.308ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.198m	5.308ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.198m	5.308ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.531m		0	1	0.00
		chip_sw_example_manufacturer	1.511m		0	1	0.00
		chip_sw_example_concurrency	4.330m	4.568ms	1	1	100.00
		chip_sw_uart_smoketest_signed	11.456s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	16.790s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.060s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.060s		0	1	0.00
V1	xbar_smoke	xbar_smoke	20.730s	62.210us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.306m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.380m	6.190ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.248m	4.407ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	56.093s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	28.739s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.209m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	56.600s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.670s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.670s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.488m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.461m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.474m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.474m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.258m	4.942ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.657m	4.874ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.253m	13.609ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.140s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	13.084s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	11.004m	17.785ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.532m	6.408ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.894m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.894m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.764s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.782m	4.452ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.782m	4.452ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.607m	18.016ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.449m	4.807ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.155m	5.435ms	1	1	100.00
		chip_sw_aes_idle	3.780m	4.576ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.270m	4.804ms	1	1	100.00
		chip_sw_kmac_idle	3.362m	3.147ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	15.399s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.601s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.884s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	14.247s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.724s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.206s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.736s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.686s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.847s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.923s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.766s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.724s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.206s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.736s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.686s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.847s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.923s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.766s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.383s		0	1	0.00
		chip_sw_aes_enc_jitter_en	45.810s	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	48.400s	10.260us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	55.890s	10.340us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.104m	10.100us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.208s		0	1	0.00
		chip_sw_clkmgr_jitter	3.666m	3.121ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.653m	5.083ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.322s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.004m	10.260us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	45.660s	10.360us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	55.270s	10.300us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	44.540s	10.180us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	48.910s	10.220us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.627s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.396s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.405s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	10.663s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	21.003m	15.475ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	7.742m	11.551ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.782m	4.452ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.000s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	7.742m	11.551ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	14.211s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	14.617s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.823s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	18.108s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	18.868s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	21.003m	15.475ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.253m	13.609ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	24.188m	20.015ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.888m	6.778ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.652m	30.018ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.158m	4.109ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	21.003m	15.475ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	10.988s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.797s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	21.003m	15.475ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	10.423s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.652m	30.018ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.716s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.181s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.259s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.383s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.216s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.501s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.797s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	20.249s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.789s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	20.249s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	20.249s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	20.249s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	5.451m	5.498ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	16.247s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.193s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.171s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	20.613s		0	1	0.00
		chip_sw_lc_ctrl_transition	20.249s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.458m	5.944ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	7.955m	14.270ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	10.252s		0	1	0.00
		chip_prim_tl_access	9.796m	16.925ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.724s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.206s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.736s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.686s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.847s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.923s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.766s		0	1	0.00
		chip_rv_dm_lc_disabled	11.004m	17.785ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.193m	4.638ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	45.810s	10.300us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.907m	5.482ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.780m	4.576ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.863m	4.485ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	48.400s	10.260us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.270m	4.804ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.592m	3.528ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.653m	4.817ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	1.104m	10.100us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.458m	5.944ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	20.249s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	44.870s	10.340us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.355m	4.234ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.362m	3.147ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.422s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.422s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.729s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.781m	5.062ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	14.649s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.458m	5.944ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	55.890s	10.340us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	10.587s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	10.383s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.155m	5.435ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.155m	5.435ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.155m	5.435ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.009m	5.689ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	7.955m	14.270ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	7.955m	14.270ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.989m	7.049ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.208s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.252s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	21.003m	15.475ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.474m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	20.249s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.009m	5.689ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.458m	5.944ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.989m	7.049ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.913m	3.388ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.009m	5.689ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.458m	5.944ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.989m	7.049ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.913m	3.388ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	20.249s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	13.347s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.789s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	16.247s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.193s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.171s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	20.613s		0	1	0.00
		chip_sw_lc_ctrl_transition	20.249s		0	1	0.00
		chip_prim_tl_access	9.796m	16.925ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	9.796m	16.925ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	12.212s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	16.706s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.396s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.383s		0	1	0.00
		chip_sw_aes_enc_jitter_en	45.810s	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	48.400s	10.260us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	55.890s	10.340us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.104m	10.100us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.208s		0	1	0.00
		chip_sw_clkmgr_jitter	3.666m	3.121ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	3.792m	5.568ms	0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	3.792m	5.568ms	0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.898m	3.739ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.833m	3.468ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.935m	4.362ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.736m	5.063ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.653m	5.130ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.966m	5.202ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.913m	3.388ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	24.188m	20.015ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	24.188m	20.015ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.716m	3.631ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.596m	3.974ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.330m	3.646ms	1	1	100.00
		chip_sw_csrng_smoketest	3.341m	4.261ms	1	1	100.00
		chip_sw_gpio_smoketest	3.314m	4.862ms	1	1	100.00
		chip_sw_hmac_smoketest	4.078m	6.174ms	1	1	100.00
		chip_sw_kmac_smoketest	4.229m	5.084ms	1	1	100.00
		chip_sw_otbn_smoketest	5.421m	6.189ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.383m	3.473ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.521m	3.942ms	1	1	100.00
		chip_sw_rv_timer_smoketest	5.023m	5.790ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.359m	3.040ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.916m	4.078ms	1	1	100.00
		chip_sw_uart_smoketest	3.231m	4.129ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	34.343s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.456s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.306m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	11.280s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.282m	4.534ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.605m	4.815ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.359m	4.251ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.224m	5.038ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	19.052s		0	1	0.00
		chip_rv_dm_lc_disabled	11.004m	17.785ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	14.050s		0	1	0.00
		chip_sw_lc_walkthrough_prod	21.291s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	14.429s		0	1	0.00
		chip_sw_lc_walkthrough_rma	12.216s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	19.052s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	35.271s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	13.560s		0	1	0.00
		rom_volatile_raw_unlock	10.548s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.423s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.664m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.987m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.822m	4.396ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.822m	4.396ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.060s		0	1	0.00
		chip_same_csr_outstanding	16.530s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.060s		0	1	0.00
		chip_same_csr_outstanding	16.530s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	20.850s	22.077us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.830s	12.808us	1	1	100.00
		xbar_smoke_large_delays	3.798m	2.076ms	1	1	100.00
		xbar_smoke_slow_rsp	5.496m	2.020ms	1	1	100.00
		xbar_random_zero_delays	13.090s	11.892us	1	1	100.00
		xbar_random_large_delays	8.204m	4.316ms	1	1	100.00
		xbar_random_slow_rsp	11.575m	4.229ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	32.440s	72.167us	1	1	100.00
		xbar_error_and_unmapped_addr	43.320s	79.806us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.317m	226.301us	1	1	100.00
		xbar_error_and_unmapped_addr	43.320s	79.806us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.179m	108.912us	1	1	100.00
		xbar_access_same_device_slow_rsp	36.554m	14.368ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	2.261m	403.425us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	8.222m	405.659us	1	1	100.00
		xbar_stress_all_with_error	3.680m	263.122us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	32.123m	5.157ms	1	1	100.00
		xbar_stress_all_with_reset_error	53.800s	81.562us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	10.429s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.163s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	10.385s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.280s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.309s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.217s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.289s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.796s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.126s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.438s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.986s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.087s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.136s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	10.670s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.011s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.319s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.492s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.300s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.556s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.095s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.526s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.578s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.602s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.099s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.321s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.403s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	13.391s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.443s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.417s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.978s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.422s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.207s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.850s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.442s		0	1	0.00
		rom_e2e_asm_init_dev	12.158s		0	1	0.00
		rom_e2e_asm_init_prod	11.841s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.121s		0	1	0.00
		rom_e2e_asm_init_rma	11.584s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.368s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.009s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.602s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.683s		0	1	0.00
V2		TOTAL			64	205	31.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.029m	4.973ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.728m	3.412ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.693s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.643s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.988s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.291s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	21.003m	15.475ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	33.710s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	16.670m	12.101ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	10.124s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.883s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.693s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.643s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.988s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.691s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.597s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.494s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.225m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	18.391m	13.686ms	1	1	100.00
		chip_plic_all_irqs_0	8.945m	5.749ms	1	1	100.00
		chip_plic_all_irqs_10	9.779m	6.765ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.484m	4.135ms	1	1	100.00
		chip_sw_dma_abort	4.814m	5.947ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.707s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.882s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.279s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.084s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	12.047s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.167s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	12.005s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.869s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.600s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	12.067s		0	1	0.00
		chip_sw_mbx_smoketest	4.306m	5.454ms	1	1	100.00
		TOTAL			75	247	30.36

Failure Buckets

Job returned non-zero exit code has 141 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.12683738552897372416029232913597450551121157591732302095688511006124227882653
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (b00d81)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (eabb1a)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 76.260s, Critical Path: 0.06s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.89065638220605332141264671807782786940728062478195910478189756855979438593449
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (54fd17)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 72.583s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.109837860363136841541505111955105490422619196298367556862060725022438148186453
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (ba2249)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 138.095s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.24274955756794520389546955038128153678325847564056539719982840196425865192846
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (9184c1)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 138.696s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.13513880708993116815347867603977780584976482355399108292676812111783761530680
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (805728)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 137.311s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 136 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.68921117930146498333061992973847507090217504394108865681554623628571189364203
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.51216530330883121226771686438922594127402676683266923166929345406728209575377
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.61320077919329356917166336600422496301478828091587336475570968864162982495346
    Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.24383069251666146032736752359774892902531834699245151161051155426907129307981
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.70818044622096130180096079456155037052517538237625431441535458257209075524978
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_rstmgr_alert_info has 1 failures.

0.chip_sw_rstmgr_alert_info.10479295292482705054427973627795877335211341082759219194677516011209915148164
Line 455, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30017.981648 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30017.981648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.105929572341475814677279694900053491093909664394196347324055065345140517041982
Line 458, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20014.672485 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20014.672485 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.109364496525748955378544850476327020513924348731821963219443734848963770727392
Line 442, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18015.976697 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18015.976697 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.48507848678378208100344774226525201663702797384077572422837138308724891158811
Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18015.954304 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18015.954304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.53095078146964929193201681312877823000042738027565934430517210691176598075717
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.4951655222829761207953271116079381223379716404307225771398653916947831285983
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.47309280259818670445554088275510553648506182198961890920922484381314137860379
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.89588859981915922237138314188821336151214150849939360485123527911318856425175
Line 482, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 5943.661040 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (38197257879758072660278787038843227619825841554357453581379224423048175409171 [0x5472e1beab8004b57286c244d9ebf7f6980d44ec3aa654f663c961e3c113d813] vs 23970371542063685751636639201307112058115176424033043240246925381924147265953 [0x34febfdf94b2d11ef9ac93039c05027726b3ecccb1d6d9dc52f85be6897581a1])
  UVM_INFO @ 5943.661040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.95036186967595145303677892302501861423669336847522576558532134177064396694803
Line 489, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 5498.440682 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (2445548352116533603178545651851118645291370003513007003824171370306825812831 [0x568219de50dc4c20a6164a7e73977c384fafdef5a420e8e6cdb9a664c26fb5f] vs 78221693924305908281963728254801550973920525560773662846243902697555821913629 [0xacefe8ea36559b30aef86936bfaef30c780414257121fb3bef5bdf67690ce61d])
  UVM_INFO @ 5498.440682 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.29220015300197823401594313763733310385605378274612116819777663553412820447899
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4942.270728 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h96f6ce33  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h0  a_user: 'h26977  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4942.270728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.7550741805077638156727477902461364647081607521159463493373182798968214496858
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4873.706534 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h9a6d1bf8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h1  a_user: 'h248de  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4873.706534 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.55741113643631167956895450741942254264711840347098481582239891686634798395586
    Line 500, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4406.836430 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4406.836430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_smoketest_sim_dv(sw/device/tests/soc_proxy_smoketest.c:34)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceTwo, kDifToggleEnabled) returns * has 1 failures:
- Test chip_sw_soc_proxy_smoketest has 1 failures.
  - 0.chip_sw_soc_proxy_smoketest.45182853134461618141225525298633993250742779454795122743284016159142181033856
    Line 449, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
```
  UVM_ERROR @ 5567.761000 us: (sw_logger_if.sv:526) [soc_proxy_smoketest_sim_dv(sw/device/tests/soc_proxy_smoketest.c:34)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceTwo, kDifToggleEnabled) returns 3
  UVM_INFO @ 5567.761000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.21982615979905817162083726356820915693002680573166183464230686527770030296637
    Line 455, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3738.713896 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3738.713896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.81562851339246416736944641306636298527326011374063872023368734488826230119248
    Line 453, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 3468.140784 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 3468.140784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.67691153477892442634605322396500887346616074970034082939938369889349289840533
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4452.285030 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4452.285030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.14978317184198915617544767489939737281155604076742561665431892579798883407740
    Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5062.702066 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5062.702066 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.78012075370799470193515134619539130376013091278817387213808687779518701797062
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.115788148013373657217936009599704688927154744236718096388386873014874613939633
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4395.745048 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4395.745048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.114138504113523268616710119978333063641865601437738643779587753828553505590143
    Line 404, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13608.611370 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13608.611370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.74907767002081365702834359625628852638110632956328567754218694641875730548638
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.13669415476530632584350127579366279504356416110530819320344498338139814917350
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5947.333380 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5947.333380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```