DMA Simulation Results

Wednesday April 30 2025 17:07:46 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	1.151ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	593.027us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	236.930us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	79.747us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	77.025us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	529.979us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	8.000s	312.550us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	27.160us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	77.025us	1	1	100.00
		dma_csr_aliasing	8.000s	312.550us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	36.000s	2.927ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	29.733m	154.190ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	16.267m	358.641ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	20.783m	415.492ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	29.733m	154.190ms	1	1	100.00
V2	dma_abort	dma_abort	19.000s	1.242ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	2.850m	30.083ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	23.599us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	216.523us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	216.523us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	79.747us	1	1	100.00
		dma_csr_rw	4.000s	77.025us	1	1	100.00
		dma_csr_aliasing	8.000s	312.550us	1	1	100.00
		dma_same_csr_outstanding	5.000s	235.462us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	79.747us	1	1	100.00
		dma_csr_rw	4.000s	77.025us	1	1	100.00
		dma_csr_aliasing	8.000s	312.550us	1	1	100.00
		dma_same_csr_outstanding	5.000s	235.462us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	18.000s	52.391us	1	1	100.00
		dma_generic_stress	20.783m	415.492ms	1	1	100.00
		dma_handshake_stress	29.733m	154.190ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	628.569us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.017m	10.944ms	1	1	100.00
		dma_longer_transfer	5.000s	123.945us	1	1	100.00
		TOTAL			21	21	100.00