EDN Simulation Results

Wednesday April 30 2025 17:07:46 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.820s 18.416us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.670s 47.935us 1 1 100.00
V1 csr_rw edn_csr_rw 1.740s 31.994us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.080s 232.167us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.940s 50.105us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.240s 78.513us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.740s 31.994us 1 1 100.00
edn_csr_aliasing 1.940s 50.105us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.720s 91.346us 1 1 100.00
V2 csrng_commands edn_genbits 1.720s 91.346us 1 1 100.00
V2 genbits edn_genbits 1.720s 91.346us 1 1 100.00
V2 interrupts edn_intr 1.730s 32.630us 1 1 100.00
V2 alerts edn_alert 1.760s 46.912us 1 1 100.00
V2 errs edn_err 1.900s 44.267us 1 1 100.00
V2 disable edn_disable 1.630s 23.634us 1 1 100.00
edn_disable_auto_req_mode 1.830s 79.381us 1 1 100.00
V2 stress_all edn_stress_all 5.250s 631.328us 1 1 100.00
V2 intr_test edn_intr_test 1.530s 35.895us 1 1 100.00
V2 alert_test edn_alert_test 2.070s 73.460us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.340s 92.112us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 3.340s 92.112us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.670s 47.935us 1 1 100.00
edn_csr_rw 1.740s 31.994us 1 1 100.00
edn_csr_aliasing 1.940s 50.105us 1 1 100.00
edn_same_csr_outstanding 1.850s 82.961us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.670s 47.935us 1 1 100.00
edn_csr_rw 1.740s 31.994us 1 1 100.00
edn_csr_aliasing 1.940s 50.105us 1 1 100.00
edn_same_csr_outstanding 1.850s 82.961us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 7.000s 1.474ms 1 1 100.00
edn_tl_intg_err 8.790s 743.701us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.780s 30.430us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.760s 46.912us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.000s 1.474ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.000s 1.474ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.000s 1.474ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.000s 1.474ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.760s 46.912us 1 1 100.00
edn_sec_cm 7.000s 1.474ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.760s 46.912us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 8.790s 743.701us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets