HMAC Simulation Results

Wednesday April 30 2025 17:07:46 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.130s 496.626us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.710s 67.009us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.560s 15.501us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 12.410s 1.401ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 7.280s 466.085us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.650s 33.076us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.560s 15.501us 1 1 100.00
hmac_csr_aliasing 7.280s 466.085us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 58.270s 1.742ms 1 1 100.00
V2 back_pressure hmac_back_pressure 48.350s 1.259ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.383m 13.275ms 1 1 100.00
hmac_test_sha384_vectors 5.744m 75.465ms 1 1 100.00
hmac_test_sha512_vectors 20.770s 253.261us 1 1 100.00
hmac_test_hmac256_vectors 5.620s 591.759us 1 1 100.00
hmac_test_hmac384_vectors 8.460s 912.364us 1 1 100.00
hmac_test_hmac512_vectors 9.970s 279.557us 1 1 100.00
V2 burst_wr hmac_burst_wr 12.390s 1.436ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 12.630m 5.286ms 1 1 100.00
V2 error hmac_error 20.820s 3.251ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.719m 10.083ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.130s 496.626us 1 1 100.00
hmac_long_msg 58.270s 1.742ms 1 1 100.00
hmac_back_pressure 48.350s 1.259ms 1 1 100.00
hmac_datapath_stress 12.630m 5.286ms 1 1 100.00
hmac_burst_wr 12.390s 1.436ms 1 1 100.00
hmac_stress_all 11.065m 98.408ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.130s 496.626us 1 1 100.00
hmac_long_msg 58.270s 1.742ms 1 1 100.00
hmac_back_pressure 48.350s 1.259ms 1 1 100.00
hmac_datapath_stress 12.630m 5.286ms 1 1 100.00
hmac_wipe_secret 1.719m 10.083ms 1 1 100.00
hmac_test_sha256_vectors 3.383m 13.275ms 1 1 100.00
hmac_test_sha384_vectors 5.744m 75.465ms 1 1 100.00
hmac_test_sha512_vectors 20.770s 253.261us 1 1 100.00
hmac_test_hmac256_vectors 5.620s 591.759us 1 1 100.00
hmac_test_hmac384_vectors 8.460s 912.364us 1 1 100.00
hmac_test_hmac512_vectors 9.970s 279.557us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.130s 496.626us 1 1 100.00
hmac_long_msg 58.270s 1.742ms 1 1 100.00
hmac_back_pressure 48.350s 1.259ms 1 1 100.00
hmac_datapath_stress 12.630m 5.286ms 1 1 100.00
hmac_burst_wr 12.390s 1.436ms 1 1 100.00
hmac_error 20.820s 3.251ms 1 1 100.00
hmac_wipe_secret 1.719m 10.083ms 1 1 100.00
hmac_test_sha256_vectors 3.383m 13.275ms 1 1 100.00
hmac_test_sha384_vectors 5.744m 75.465ms 1 1 100.00
hmac_test_sha512_vectors 20.770s 253.261us 1 1 100.00
hmac_test_hmac256_vectors 5.620s 591.759us 1 1 100.00
hmac_test_hmac384_vectors 8.460s 912.364us 1 1 100.00
hmac_test_hmac512_vectors 9.970s 279.557us 1 1 100.00
hmac_stress_all 11.065m 98.408ms 1 1 100.00
V2 stress_all hmac_stress_all 11.065m 98.408ms 1 1 100.00
V2 alert_test hmac_alert_test 1.580s 69.384us 1 1 100.00
V2 intr_test hmac_intr_test 1.390s 14.692us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.410s 309.983us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.410s 309.983us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.710s 67.009us 1 1 100.00
hmac_csr_rw 1.560s 15.501us 1 1 100.00
hmac_csr_aliasing 7.280s 466.085us 1 1 100.00
hmac_same_csr_outstanding 2.640s 478.542us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.710s 67.009us 1 1 100.00
hmac_csr_rw 1.560s 15.501us 1 1 100.00
hmac_csr_aliasing 7.280s 466.085us 1 1 100.00
hmac_same_csr_outstanding 2.640s 478.542us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.050s 390.551us 1 1 100.00
hmac_tl_intg_err 2.480s 97.110us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.480s 97.110us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.130s 496.626us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.130s 157.912us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 3.368m 8.406ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.570s 8.299us 1 1 100.00
TOTAL 28 28 100.00