I2C Simulation Results

Wednesday April 30 2025 17:07:46 UTC

GitHub Revision: `35aa874`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	25.350s	8.256ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.300s	2.172ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.570s	23.875us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.540s	49.420us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.090s	462.248us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.900s	171.954us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.830s	137.143us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.540s	49.420us	1	1	100.00
		i2c_csr_aliasing	1.900s	171.954us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	4.410s	297.775us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	8.868m	67.141ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	23.230s	6.763ms	1	1	100.00
V2	host_override	i2c_host_override	1.610s	26.230us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.050m	3.821ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	42.120s	2.103ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.070s	298.358us	1	1	100.00
		i2c_host_fifo_fmt_empty	10.470s	567.130us	1	1	100.00
		i2c_host_fifo_reset_rx	7.650s	2.270ms	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.598m	11.188ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	6.950s	461.498us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.020s	97.580us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.410s	7.275ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	26.380s	7.062ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.490s	895.193us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	7.800s	499.247us	1	1	100.00
		i2c_target_intr_smoke	5.200s	2.103ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.100s	2.434ms	1	1	100.00
		i2c_target_fifo_reset_tx	1.880s	320.441us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	26.820s	33.756ms	1	1	100.00
		i2c_target_stress_rd	7.800s	499.247us	1	1	100.00
		i2c_target_intr_stress_wr	1.693m	23.965ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.250s	5.337ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	17.750s	4.669ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.690s	2.957ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.510s	1.920ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.670s	2.375ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.120s	400.219us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	23.230s	6.763ms	1	1	100.00
		i2c_host_perf_precise	2.130s	85.251us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	6.950s	461.498us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.440s	84.132us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.980s	5.314ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.880s	542.084us	1	1	100.00
		i2c_target_nack_txstretch	2.140s	269.220us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.280s	1.899ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.330s	555.248us	1	1	100.00
V2	alert_test	i2c_alert_test	1.530s	23.135us	1	1	100.00
V2	intr_test	i2c_intr_test	1.580s	253.269us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.520s	342.067us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.520s	342.067us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.570s	23.875us	1	1	100.00
		i2c_csr_rw	1.540s	49.420us	1	1	100.00
		i2c_csr_aliasing	1.900s	171.954us	1	1	100.00
		i2c_same_csr_outstanding	1.800s	63.793us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.570s	23.875us	1	1	100.00
		i2c_csr_rw	1.540s	49.420us	1	1	100.00
		i2c_csr_aliasing	1.900s	171.954us	1	1	100.00
		i2c_same_csr_outstanding	1.800s	63.793us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	2.570s	241.478us	1	1	100.00
		i2c_sec_cm	1.720s	134.828us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.570s	241.478us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	2.850s	274.885us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.930s	1.414ms	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	23.390s	921.942us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.1102804072827142932771794605345736494295121713216141407581273026215919943143
    Line 93, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 274884758 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 274884758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.108630590879774430444955203507296617811182210113948108531855858968030051700810
    Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 921942309 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 921942309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.66443020045194954190033516373572131203974139202519681508342648437742794165016
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1414220867 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1414220867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.80080737645902948615181204594197291940334360836634881841959574662865960814605
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  97580184 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @13877