KEYMGR Simulation Results

Wednesday April 30 2025 17:07:46 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.990s	312.067us	1	1	100.00
V1	random	keymgr_random	34.640s	2.351ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.750s	40.224us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.810s	49.968us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	6.940s	1.965ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	3.690s	259.049us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.710s	12.775us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.810s	49.968us	1	1	100.00
		keymgr_csr_aliasing	3.690s	259.049us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	23.770s	628.901us	1	1	100.00
V2	sideload	keymgr_sideload	12.470s	2.667ms	1	1	100.00
		keymgr_sideload_kmac	2.220s	20.828us	1	1	100.00
		keymgr_sideload_aes	2.810s	161.153us	1	1	100.00
		keymgr_sideload_otbn	2.890s	38.130us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.750s	471.118us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.990s	446.183us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.020s	590.059us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.070s	403.090us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.670s	33.838us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.000s	75.750us	1	1	100.00
V2	stress_all	keymgr_stress_all	16.940s	3.534ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.680s	71.367us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.500s	17.851us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.670s	993.965us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.670s	993.965us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.750s	40.224us	1	1	100.00
		keymgr_csr_rw	1.810s	49.968us	1	1	100.00
		keymgr_csr_aliasing	3.690s	259.049us	1	1	100.00
		keymgr_same_csr_outstanding	2.380s	123.340us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.750s	40.224us	1	1	100.00
		keymgr_csr_rw	1.810s	49.968us	1	1	100.00
		keymgr_csr_aliasing	3.690s	259.049us	1	1	100.00
		keymgr_same_csr_outstanding	2.380s	123.340us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	5.390s	583.050us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	5.390s	583.050us	1	1	100.00
		keymgr_tl_intg_err	6.860s	2.840ms	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.030s	460.230us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.030s	460.230us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.030s	460.230us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.030s	460.230us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.630s	395.572us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	5.390s	583.050us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	5.390s	583.050us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	6.860s	2.840ms	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.030s	460.230us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	23.770s	628.901us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	34.640s	2.351ms	1	1	100.00
		keymgr_csr_rw	1.810s	49.968us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	34.640s	2.351ms	1	1	100.00
		keymgr_csr_rw	1.810s	49.968us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	34.640s	2.351ms	1	1	100.00
		keymgr_csr_rw	1.810s	49.968us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.990s	446.183us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.670s	33.838us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.670s	33.838us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	34.640s	2.351ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.270s	109.326us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	5.390s	583.050us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	5.390s	583.050us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	5.390s	583.050us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	4.330s	574.287us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.990s	446.183us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	5.390s	583.050us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	5.390s	583.050us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	5.390s	583.050us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	4.330s	574.287us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	4.330s	574.287us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	5.390s	583.050us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	4.330s	574.287us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	5.390s	583.050us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	4.330s	574.287us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	12.920s	299.793us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	30	93.33

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.8420442748722580573426488314382782569382100429566854747190185436423401852668
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
        UVM_ERROR @ 123340319 ps: (keymgr_csr_assert_fpv.sv:421) [ASSERT FAILED] sealing_sw_binding_6_rd_A
        UVM_INFO @ 123340319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.43654764678115494255581824789585239552316791712875275747175661895102486092422
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
        UVM_ERROR @  12774532 ps: (keymgr_csr_assert_fpv.sv:431) [ASSERT FAILED] attest_sw_binding_0_rd_A
        UVM_INFO @  12774532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---