| V1 |
smoke |
keymgr_dpe_smoke |
6.780s |
507.436us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
2.170s |
78.923us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.850s |
20.214us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
17.390s |
3.421ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
4.830s |
76.606us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.820s |
30.076us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.850s |
20.214us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.830s |
76.606us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.550s |
9.902us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.790s |
30.444us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
3.060s |
166.219us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
3.060s |
166.219us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
2.170s |
78.923us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.850s |
20.214us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.830s |
76.606us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.260s |
131.999us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
2.170s |
78.923us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.850s |
20.214us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.830s |
76.606us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.260s |
131.999us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
6.630s |
1.298ms |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
2.900s |
330.671us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
4.070s |
327.016us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
4.070s |
327.016us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
4.070s |
327.016us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
4.070s |
327.016us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
3.940s |
436.157us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
6.630s |
1.298ms |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
6.630s |
1.298ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |