KMAC/MASKED Simulation Results

Wednesday April 30 2025 17:07:46 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	17.440s	1.103ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.880s	58.766us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.750s	21.437us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.250s	150.906us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.300s	496.617us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.010s	91.832us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.750s	21.437us	1	1	100.00
		kmac_csr_aliasing	7.300s	496.617us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.640s	16.294us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.180s	15.646us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	31.684m	90.651ms	1	1	100.00
V2	burst_write	kmac_burst_write	2.223m	18.239ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.930s	4.120ms	1	1	100.00
		kmac_test_vectors_sha3_256	27.290s	2.435ms	1	1	100.00
		kmac_test_vectors_sha3_384	24.396m	86.350ms	1	1	100.00
		kmac_test_vectors_sha3_512	17.180s	1.349ms	1	1	100.00
		kmac_test_vectors_shake_128	27.744m	32.371ms	1	1	100.00
		kmac_test_vectors_shake_256	5.149m	72.957ms	1	1	100.00
		kmac_test_vectors_kmac	3.010s	140.914us	1	1	100.00
		kmac_test_vectors_kmac_xof	4.170s	128.701us	1	1	100.00
V2	sideload	kmac_sideload	3.870m	10.680ms	1	1	100.00
V2	app	kmac_app	1.941m	24.139ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.706m	9.916ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.298m	34.274ms	1	1	100.00
V2	error	kmac_error	3.836m	12.988ms	1	1	100.00
V2	key_error	kmac_key_error	9.830s	5.466ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.530s	143.243us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	9.530s	176.731us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.700s	38.041us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	5.470s	1.133ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.210s	97.996us	1	1	100.00
V2	stress_all	kmac_stress_all	13.455m	31.184ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.650s	32.569us	1	1	100.00
V2	alert_test	kmac_alert_test	1.830s	36.692us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.120s	678.250us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.120s	678.250us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.880s	58.766us	1	1	100.00
		kmac_csr_rw	1.750s	21.437us	1	1	100.00
		kmac_csr_aliasing	7.300s	496.617us	1	1	100.00
		kmac_same_csr_outstanding	2.300s	282.897us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.880s	58.766us	1	1	100.00
		kmac_csr_rw	1.750s	21.437us	1	1	100.00
		kmac_csr_aliasing	7.300s	496.617us	1	1	100.00
		kmac_same_csr_outstanding	2.300s	282.897us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.900s	73.529us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.900s	73.529us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.900s	73.529us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.900s	73.529us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.810s	25.134us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	37.190s	3.928ms	1	1	100.00
		kmac_tl_intg_err	2.830s	82.441us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.830s	82.441us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.210s	97.996us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	17.440s	1.103ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.870m	10.680ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.900s	73.529us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	37.190s	3.928ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	37.190s	3.928ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	37.190s	3.928ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	17.440s	1.103ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.210s	97.996us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	37.190s	3.928ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.723m	6.700ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	17.440s	1.103ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.681m	16.766ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.61097658117693497449730612824485596223595680622561247607662344803390992352880
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
        UVM_ERROR @  25134425 ps: (kmac_csr_assert_fpv.sv:537) [ASSERT FAILED] prefix_9_rd_A
        UVM_INFO @  25134425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---