KMAC/UNMASKED Simulation Results

Wednesday April 30 2025 17:07:46 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	3.600s	403.045us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.750s	118.488us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.790s	19.516us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.120s	552.377us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.190s	4.217ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.160s	148.288us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.790s	19.516us	1	1	100.00
		kmac_csr_aliasing	7.190s	4.217ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.650s	31.613us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.900s	41.295us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	32.480m	623.444ms	1	1	100.00
V2	burst_write	kmac_burst_write	10.745m	332.677ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	18.312m	18.538ms	1	1	100.00
		kmac_test_vectors_sha3_256	29.090s	2.376ms	1	1	100.00
		kmac_test_vectors_sha3_384	13.407m	12.693ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.230s	1.121ms	1	1	100.00
		kmac_test_vectors_shake_128	1.914m	14.252ms	1	1	100.00
		kmac_test_vectors_shake_256	1.290m	4.737ms	1	1	100.00
		kmac_test_vectors_kmac	2.950s	339.979us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.520s	52.634us	1	1	100.00
V2	sideload	kmac_sideload	3.925m	18.652ms	1	1	100.00
V2	app	kmac_app	2.837m	41.424ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.488m	16.947ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.037m	29.437ms	1	1	100.00
V2	error	kmac_error	44.930s	946.664us	1	1	100.00
V2	key_error	kmac_key_error	9.530s	4.722ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.550s	343.751us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	5.940s	89.548us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	8.910s	1.634ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	26.680s	34.830ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.930s	63.757us	1	1	100.00
V2	stress_all	kmac_stress_all	15.379m	42.260ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.550s	16.642us	1	1	100.00
V2	alert_test	kmac_alert_test	1.760s	21.773us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.240s	286.223us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.240s	286.223us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.750s	118.488us	1	1	100.00
		kmac_csr_rw	1.790s	19.516us	1	1	100.00
		kmac_csr_aliasing	7.190s	4.217ms	1	1	100.00
		kmac_same_csr_outstanding	2.880s	112.026us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.750s	118.488us	1	1	100.00
		kmac_csr_rw	1.790s	19.516us	1	1	100.00
		kmac_csr_aliasing	7.190s	4.217ms	1	1	100.00
		kmac_same_csr_outstanding	2.880s	112.026us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.200s	182.897us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.200s	182.897us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.200s	182.897us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.200s	182.897us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.820s	86.610us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	21.420s	4.644ms	1	1	100.00
		kmac_tl_intg_err	1.890s	44.023us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.890s	44.023us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.930s	63.757us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	3.600s	403.045us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.925m	18.652ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.200s	182.897us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	21.420s	4.644ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	21.420s	4.644ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	21.420s	4.644ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	3.600s	403.045us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.930s	63.757us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	21.420s	4.644ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.756m	35.783ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	3.600s	403.045us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	59.750s	36.336ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.21434150143249635532940492823555535829908501539729072367828501507854495948860
      Line 157, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 36336101586 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 36336101586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.90223165640348214503748417205911226331084492088448833167976545724686518605179
      Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
        UVM_ERROR @  44023079 ps: (kmac_csr_assert_fpv.sv:522) [ASSERT FAILED] prefix_6_rd_A
        UVM_INFO @  44023079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---