OTBN Simulation Results

Wednesday April 30 2025 17:07:46 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	40.717us	1	1	100.00
V1	single_binary	otbn_single	8.000s	26.223us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	21.551us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	35.495us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	111.756us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	50.267us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	24.950us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	35.495us	1	1	100.00
		otbn_csr_aliasing	6.000s	50.267us	1	1	100.00
V1	mem_walk	otbn_mem_walk	13.000s	184.834us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	14.000s	168.498us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	26.000s	1.056ms	1	1	100.00
V2	multi_error	otbn_multi_err	49.000s	146.139us	1	1	100.00
V2	back_to_back	otbn_multi	1.067m	743.311us	1	1	100.00
V2	stress_all	otbn_stress_all	39.000s	136.655us	1	1	100.00
V2	lc_escalation	otbn_escalate	11.000s	31.078us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	54.066us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	7.000s	21.700us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	22.326us	1	1	100.00
V2	intr_test	otbn_intr_test	5.000s	31.077us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	67.106us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	67.106us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	21.551us	1	1	100.00
		otbn_csr_rw	6.000s	35.495us	1	1	100.00
		otbn_csr_aliasing	6.000s	50.267us	1	1	100.00
		otbn_same_csr_outstanding	5.000s	54.301us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	21.551us	1	1	100.00
		otbn_csr_rw	6.000s	35.495us	1	1	100.00
		otbn_csr_aliasing	6.000s	50.267us	1	1	100.00
		otbn_same_csr_outstanding	5.000s	54.301us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	8.000s	28.093us	1	1	100.00
		otbn_dmem_err	9.000s	70.286us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	48.012us	1	1	100.00
		otbn_controller_ispr_rdata_err	8.000s	50.645us	1	1	100.00
		otbn_mac_bignum_acc_err	12.000s	98.816us	1	1	100.00
		otbn_urnd_err	11.000s	24.077us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	51.857us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	13.836us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	23.938us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	3.217m	2.221ms	1	1	100.00
		otbn_tl_intg_err	19.000s	105.819us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	26.000s	629.589us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	3.217m	2.221ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	3.217m	2.221ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	40.717us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	9.000s	70.286us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	8.000s	28.093us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	19.000s	105.819us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	11.000s	31.078us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	8.000s	28.093us	1	1	100.00
		otbn_dmem_err	9.000s	70.286us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	54.066us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	51.857us	1	1	100.00
		otbn_sec_cm	3.217m	2.221ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	3.217m	2.221ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	8.000s	26.223us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	8.000s	28.093us	1	1	100.00
		otbn_dmem_err	9.000s	70.286us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	54.066us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	51.857us	1	1	100.00
		otbn_sec_cm	3.217m	2.221ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	3.217m	2.221ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	11.000s	31.078us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	8.000s	28.093us	1	1	100.00
		otbn_dmem_err	9.000s	70.286us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	54.066us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	51.857us	1	1	100.00
		otbn_sec_cm	3.217m	2.221ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	3.217m	2.221ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	8.000s	26.223us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	92.666us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	13.000s	32.087us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.800m	1.094ms	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.800m	1.094ms	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	32.604us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	3.217m	2.221ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	3.217m	2.221ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	14.000s	64.474us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	3.217m	2.221ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	3.217m	2.221ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	38.297us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	38.297us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	61.349us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	8.000s	26.223us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	8.000s	26.223us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	8.000s	26.223us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.067m	743.311us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	8.000s	26.223us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	8.000s	26.223us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	41.955us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	8.000s	26.223us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	3.217m	2.221ms	1	1	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	25.000s	139.305us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.96220229559883279747237586997195921142709929775011252552469395875020798335819
      Line 142, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 139304669 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 139304669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.43773824806381579533434703528555560276229793835695032840663967640692836308506
      Line 107, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 61349461 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  61349461 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  61349461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---