ROM_CTRL/32KB Simulation Results

Wednesday April 30 2025 17:07:46 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 6.650s 141.235us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.000s 285.501us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.620s 1.062ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.780s 127.261us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.840s 373.056us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.760s 133.990us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.620s 1.062ms 1 1 100.00
rom_ctrl_csr_aliasing 5.840s 373.056us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.650s 168.359us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.420s 1.795ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.950s 1.054ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 16.970s 1.659ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 8.750s 223.974us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.950s 169.473us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.290s 384.912us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.290s 384.912us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.000s 285.501us 1 1 100.00
rom_ctrl_csr_rw 5.620s 1.062ms 1 1 100.00
rom_ctrl_csr_aliasing 5.840s 373.056us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.950s 388.020us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.000s 285.501us 1 1 100.00
rom_ctrl_csr_rw 5.620s 1.062ms 1 1 100.00
rom_ctrl_csr_aliasing 5.840s 373.056us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.950s 388.020us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 18.360s 8.353ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.995m 635.851us 1 1 100.00
rom_ctrl_tl_intg_err 41.110s 2.523ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.995m 635.851us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.995m 635.851us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.995m 635.851us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.995m 635.851us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 6.650s 141.235us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 6.650s 141.235us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 6.650s 141.235us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 41.110s 2.523ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_kmac_err_chk 8.750s 223.974us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 18.360s 8.353ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.995m 635.851us 1 1 100.00
V2S TOTAL 3 4 75.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 59.850s 2.188ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 18 19 94.74

Failure Buckets