RV_TIMER Simulation Results

Wednesday April 30 2025 17:07:46 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.570s	33.743us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.520s	70.017us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.450s	13.034us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.420s	291.534us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.830s	69.559us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.630s	93.745us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.450s	13.034us	1	1	100.00
		rv_timer_csr_aliasing	1.830s	69.559us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	2.000s	890.343us	1	1	100.00
V2	disabled	rv_timer_disabled	14.940s	17.277ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	54.200s	43.780ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	54.200s	43.780ms	1	1	100.00
V2	stress	rv_timer_stress_all	29.560s	24.019ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.670s	57.705us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.480s	14.017us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.340s	23.557us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.340s	23.557us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.520s	70.017us	1	1	100.00
		rv_timer_csr_rw	1.450s	13.034us	1	1	100.00
		rv_timer_csr_aliasing	1.830s	69.559us	1	1	100.00
		rv_timer_same_csr_outstanding	1.930s	102.450us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.520s	70.017us	1	1	100.00
		rv_timer_csr_rw	1.450s	13.034us	1	1	100.00
		rv_timer_csr_aliasing	1.830s	69.559us	1	1	100.00
		rv_timer_same_csr_outstanding	1.930s	102.450us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.920s	230.554us	1	1	100.00
		rv_timer_tl_intg_err	1.810s	101.922us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.810s	101.922us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	38.780s	4.989ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			17	17	100.00