SPI_DEVICE/1R1W Simulation Results

Wednesday April 30 2025 17:07:46 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.110m	40.194ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.860s	88.877us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.950s	74.016us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.470s	1.628ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.780s	216.991us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.240s	62.056us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.950s	74.016us	1	1	100.00
		spi_device_csr_aliasing	10.780s	216.991us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.640s	27.024us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.550s	70.857us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.720s	172.197us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.640s	957.037ns	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.560s	1.687us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.740s	137.479us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.740s	137.479us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	6.790s	1.700ms	1	1	100.00
		spi_device_tpm_sts_read	1.690s	29.547us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	16.750s	3.995ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.090s	3.833ms	1	1	100.00
		spi_device_flash_all	4.368m	61.384ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.170s	2.067ms	1	1	100.00
		spi_device_flash_all	4.368m	61.384ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.170s	2.067ms	1	1	100.00
		spi_device_flash_all	4.368m	61.384ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	4.368m	61.384ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.600s	76.847us	1	1	100.00
		spi_device_flash_all	4.368m	61.384ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.600s	76.847us	1	1	100.00
		spi_device_flash_all	4.368m	61.384ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.600s	76.847us	1	1	100.00
		spi_device_flash_all	4.368m	61.384ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.600s	76.847us	1	1	100.00
		spi_device_flash_all	4.368m	61.384ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.600s	76.847us	1	1	100.00
		spi_device_flash_all	4.368m	61.384ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	11.370s	19.665ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	41.620s	105.928ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	41.620s	105.928ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	41.620s	105.928ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	5.470s	162.789us	1	1	100.00
		spi_device_read_buffer_direct	5.590s	469.741us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	41.620s	105.928ms	1	1	100.00
		spi_device_flash_all	4.368m	61.384ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	4.368m	61.384ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	4.368m	61.384ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.860s	167.461us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.860s	167.461us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.110m	40.194ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.678m	71.610ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.925m	414.277ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.970s	46.900us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.680s	36.168us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.170s	658.561us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.170s	658.561us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.860s	88.877us	1	1	100.00
		spi_device_csr_rw	1.950s	74.016us	1	1	100.00
		spi_device_csr_aliasing	10.780s	216.991us	1	1	100.00
		spi_device_same_csr_outstanding	2.870s	160.868us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.860s	88.877us	1	1	100.00
		spi_device_csr_rw	1.950s	74.016us	1	1	100.00
		spi_device_csr_aliasing	10.780s	216.991us	1	1	100.00
		spi_device_same_csr_outstanding	2.870s	160.868us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.150s	534.157us	1	1	100.00
		spi_device_tl_intg_err	11.530s	544.410us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.530s	544.410us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	40.220s	3.796ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.42175617514958091441111695471174198797144057911432533955218059591212112353763
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    769531 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[46])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    769531 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    769531 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[942])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.89880670654266194914463563792517285467015523008010456307157985041095390282794
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1059020 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1059020 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1091020 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x57e27 [1010111111000100111] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1091020 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x57e27 [1010111111000100111] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])