SRAM_CTRL/MAIN Simulation Results

Wednesday April 30 2025 17:07:46 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	16.030s	2.546ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.460s	33.951us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.660s	12.652us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.050s	262.091us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.700s	14.056us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.200s	694.723us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.660s	12.652us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	14.056us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.652m	43.765ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.621m	3.994ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.739m	2.869ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.285m	44.933ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	16.082m	82.878ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	43.820s	5.178ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	41.180s	48.916ms	1	1	100.00
V2	executable	sram_ctrl_executable	1.343m	19.931ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	30.450s	806.897us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.031m	15.429ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	51.140s	2.567ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	6.900s	1.408ms	1	1	100.00
		sram_ctrl_throughput_w_readback	4.670s	1.867ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.868m	43.365ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.130s	3.341ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	35.544m	32.874ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.370s	28.729us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.390s	41.198us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.390s	41.198us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.460s	33.951us	1	1	100.00
		sram_ctrl_csr_rw	1.660s	12.652us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	14.056us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.710s	171.727us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.460s	33.951us	1	1	100.00
		sram_ctrl_csr_rw	1.660s	12.652us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	14.056us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.710s	171.727us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	28.210s	7.519ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.450s	3.627us	0	1	0.00
		sram_ctrl_tl_intg_err	2.750s	245.566us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.450s	3.627us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.750s	245.566us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.868m	43.365ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.868m	43.365ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.660s	12.652us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.343m	19.931ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.343m	19.931ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.343m	19.931ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	41.180s	48.916ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.890s	671.981us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	28.210s	7.519ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.500s	2.432ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	16.030s	2.546ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	16.030s	2.546ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.343m	19.931ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.450s	3.627us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	41.180s	48.916ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.450s	3.627us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.450s	3.627us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	16.030s	2.546ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.450s	3.627us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.184m	1.492ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.20397906184510294496353617834670822167912281303364349598513852263796269741444
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2432396296 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x55) != exp (0x31)
        UVM_INFO @ 2432396296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.23843686670047395654157112345689452794222229315734613038712953596592510675445
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @   3626945 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @   3626945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---