SRAM_CTRL/RET Simulation Results

Wednesday April 30 2025 17:07:46 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	25.310s	221.449us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.380s	33.321us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.690s	16.901us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.860s	356.017us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.780s	25.576us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.780s	75.125us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.690s	16.901us	1	1	100.00
		sram_ctrl_csr_aliasing	1.780s	25.576us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.440s	232.621us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.420s	225.656us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.307m	6.272ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.833m	2.550ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	47.190s	4.891ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.245m	12.672ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.070s	91.082us	1	1	100.00
V2	executable	sram_ctrl_executable	9.002m	59.814ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	36.610s	3.000ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.169m	6.003ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	12.530s	265.670us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	8.060s	78.579us	1	1	100.00
		sram_ctrl_throughput_w_readback	34.930s	467.383us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.041m	7.738ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.730s	83.589us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	17.394m	268.357ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.550s	17.840us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.470s	656.348us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.470s	656.348us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.380s	33.321us	1	1	100.00
		sram_ctrl_csr_rw	1.690s	16.901us	1	1	100.00
		sram_ctrl_csr_aliasing	1.780s	25.576us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.640s	21.265us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.380s	33.321us	1	1	100.00
		sram_ctrl_csr_rw	1.690s	16.901us	1	1	100.00
		sram_ctrl_csr_aliasing	1.780s	25.576us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.640s	21.265us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.330s	380.007us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.600s	4.064us	0	1	0.00
		sram_ctrl_tl_intg_err	2.590s	728.166us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.600s	4.064us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.590s	728.166us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.041m	7.738ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.041m	7.738ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.690s	16.901us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	9.002m	59.814ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	9.002m	59.814ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	9.002m	59.814ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.070s	91.082us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.680s	202.198us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.330s	380.007us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.010s	50.453us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	25.310s	221.449us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	25.310s	221.449us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	9.002m	59.814ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.600s	4.064us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.070s	91.082us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.600s	4.064us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.600s	4.064us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	25.310s	221.449us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.600s	4.064us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.670s	244.967us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.95059441705843182940406023138264681439593857942480712484395549689921099282296
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4063748 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4063748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---