UART Simulation Results

Wednesday April 30 2025 17:07:46 UTC

GitHub Revision: 35aa874

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.490s	903.510us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.390s	26.857us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.530s	29.823us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.040s	401.711us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.520s	14.637us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.800s	89.727us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.530s	29.823us	1	1	100.00
		uart_csr_aliasing	1.520s	14.637us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	9.700s	45.646ms	1	1	100.00
V2	parity	uart_smoke	2.490s	903.510us	1	1	100.00
		uart_tx_rx	9.700s	45.646ms	1	1	100.00
V2	parity_error	uart_intr	4.400s	9.280ms	1	1	100.00
		uart_rx_parity_err	6.890s	21.217ms	1	1	100.00
V2	watermark	uart_tx_rx	9.700s	45.646ms	1	1	100.00
		uart_intr	4.400s	9.280ms	1	1	100.00
V2	fifo_full	uart_fifo_full	15.810s	56.675ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	31.890s	54.087ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	38.950s	307.152ms	1	1	100.00
V2	rx_frame_err	uart_intr	4.400s	9.280ms	1	1	100.00
V2	rx_break_err	uart_intr	4.400s	9.280ms	1	1	100.00
V2	rx_timeout	uart_intr	4.400s	9.280ms	1	1	100.00
V2	perf	uart_perf	10.096m	32.572ms	1	1	100.00
V2	sys_loopback	uart_loopback	5.520s	9.161ms	1	1	100.00
V2	line_loopback	uart_loopback	5.520s	9.161ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	32.290s	39.575ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	5.820s	4.157ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.030s	1.651ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	23.760s	4.964ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	9.282m	143.578ms	1	1	100.00
V2	stress_all	uart_stress_all	34.522m	183.167ms	1	1	100.00
V2	alert_test	uart_alert_test	1.410s	68.921us	1	1	100.00
V2	intr_test	uart_intr_test	1.410s	14.545us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.800s	772.558us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.800s	772.558us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.390s	26.857us	1	1	100.00
		uart_csr_rw	1.530s	29.823us	1	1	100.00
		uart_csr_aliasing	1.520s	14.637us	1	1	100.00
		uart_same_csr_outstanding	1.500s	62.266us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.390s	26.857us	1	1	100.00
		uart_csr_rw	1.530s	29.823us	1	1	100.00
		uart_csr_aliasing	1.520s	14.637us	1	1	100.00
		uart_same_csr_outstanding	1.500s	62.266us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.750s	264.577us	1	1	100.00
		uart_tl_intg_err	2.030s	176.195us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.030s	176.195us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	44.260s	12.296ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00