CHIP Simulation Results

Wednesday April 30 2025 17:07:46 UTC

GitHub Revision: `35aa874`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.189m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.189m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	23.301s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	14.364s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	12.398s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.584m	5.811ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.584m	5.811ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.584m	5.811ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.603m		0	1	0.00
		chip_sw_example_manufacturer	1.555m		0	1	0.00
		chip_sw_example_concurrency	3.662m	4.776ms	1	1	100.00
		chip_sw_uart_smoketest_signed	14.376s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.170s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.070s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.070s		0	1	0.00
V1	xbar_smoke	xbar_smoke	9.520s	12.826us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.226m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.450m	10.469ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.258m	3.997ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	12.563s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	12.035s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	12.369s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	13.653s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.660s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.660s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.600m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.468m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.139m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.139m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.985m	4.654ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.772m	5.208ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.708m	13.711ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.696s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.549s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	9.792m	9.792ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.652m	5.664ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	22.799m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	22.799m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.695s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.512m	5.556ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.512m	5.556ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.959m	18.021ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.748m	5.265ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.322m	4.965ms	1	1	100.00
		chip_sw_aes_idle	4.250m	5.121ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.981m	4.978ms	1	1	100.00
		chip_sw_kmac_idle	3.724m	3.871ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	16.842s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.295s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.651s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	10.069s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	10.526s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.143s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.041s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.526s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.366s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.094s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.459s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.526s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.143s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.041s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.526s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.366s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.094s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.459s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.161s		0	1	0.00
		chip_sw_aes_enc_jitter_en	45.830s	10.260us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	47.370s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	53.570s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.060s	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.316s		0	1	0.00
		chip_sw_clkmgr_jitter	3.424m	4.851ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.458m	4.166ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.760s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	46.700s	10.340us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	46.670s	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	47.870s	10.400us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	45.660s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	54.470s	10.100us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.057s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.998s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.623s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	10.739s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	19.756m	16.453ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.784m	9.576ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.512m	5.556ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.671s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.784m	9.576ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	15.227s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	11.735s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.555s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	12.524s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.166s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	19.756m	16.453ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.708m	13.711ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	22.978m	20.017ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.545m	9.320ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	10.883m	30.016ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.497m	5.278ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	19.756m	16.453ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.608s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.853s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	19.756m	16.453ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.125s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	10.883m	30.016ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	14.499s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.920s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	14.953s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.262s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.751s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	13.299s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.853s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	17.920s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	20.029s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	17.920s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	17.920s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	17.920s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.470m	6.530ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.797s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.467s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	16.919s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	11.923s		0	1	0.00
		chip_sw_lc_ctrl_transition	17.920s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.853m	8.856ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.789m	12.216ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.057s		0	1	0.00
		chip_prim_tl_access	19.138m	32.088ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.526s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.143s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.041s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.526s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.366s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.094s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.459s		0	1	0.00
		chip_rv_dm_lc_disabled	9.792m	9.792ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.605m	5.624ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	45.830s	10.260us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.743m	4.633ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.250m	5.121ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.174m	5.388ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	47.370s	10.240us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.981m	4.978ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.043m	4.990ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.248m	4.649ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	49.060s	10.220us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.853m	8.856ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	17.920s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	43.850s	10.160us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.611m	4.798ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.724m	3.871ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.978s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.978s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.048s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.430m	5.212ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	17.452s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.853m	8.856ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	53.570s	10.240us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	11.386s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	14.161s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.322m	4.965ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.322m	4.965ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.322m	4.965ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	6.979m	5.824ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.789m	12.216ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.789m	12.216ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.935m	6.767ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.316s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.057s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	19.756m	16.453ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.139m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	17.920s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	6.979m	5.824ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.853m	8.856ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	6.935m	6.767ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.392m	5.670ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	6.979m	5.824ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.853m	8.856ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	6.935m	6.767ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.392m	5.670ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	17.920s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.123s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	20.029s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.797s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.467s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	16.919s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	11.923s		0	1	0.00
		chip_sw_lc_ctrl_transition	17.920s		0	1	0.00
		chip_prim_tl_access	19.138m	32.088ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	19.138m	32.088ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	13.919s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	15.986s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.998s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.161s		0	1	0.00
		chip_sw_aes_enc_jitter_en	45.830s	10.260us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	47.370s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	53.570s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.060s	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.316s		0	1	0.00
		chip_sw_clkmgr_jitter	3.424m	4.851ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	3.526m	5.536ms	0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	3.526m	5.536ms	0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.284m	5.648ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	5.004m	4.696ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.909m	3.531ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.830m	5.013ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.154m	5.933ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.848m	3.200ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.392m	5.670ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	22.978m	20.017ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	22.978m	20.017ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.216m	4.454ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.528m	3.453ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.199m	4.627ms	1	1	100.00
		chip_sw_csrng_smoketest	3.375m	4.117ms	1	1	100.00
		chip_sw_gpio_smoketest	3.156m	3.300ms	1	1	100.00
		chip_sw_hmac_smoketest	3.462m	4.514ms	1	1	100.00
		chip_sw_kmac_smoketest	4.061m	3.625ms	1	1	100.00
		chip_sw_otbn_smoketest	5.861m	6.530ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.863m	4.458ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.855m	3.922ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.236m	6.978ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.692m	4.960ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.482m	4.067ms	1	1	100.00
		chip_sw_uart_smoketest	3.641m	5.108ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.429s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	14.376s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.226m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	10.382s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.605m	4.087ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.801m	6.331ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.587m	4.602ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.490m	4.303ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.486s		0	1	0.00
		chip_rv_dm_lc_disabled	9.792m	9.792ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.144s		0	1	0.00
		chip_sw_lc_walkthrough_prod	12.777s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	17.612s		0	1	0.00
		chip_sw_lc_walkthrough_rma	14.725s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.486s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.156s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.345s		0	1	0.00
		rom_volatile_raw_unlock	11.169s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	15.241s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	58.706s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.193m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.478m	4.116ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.478m	4.116ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.070s		0	1	0.00
		chip_same_csr_outstanding	10.910s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.070s		0	1	0.00
		chip_same_csr_outstanding	10.910s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	2.614m	485.255us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.230s	12.417us	1	1	100.00
		xbar_smoke_large_delays	4.647m	2.419ms	1	1	100.00
		xbar_smoke_slow_rsp	5.855m	2.148ms	1	1	100.00
		xbar_random_zero_delays	42.730s	38.792us	1	1	100.00
		xbar_random_large_delays	22.478m	11.714ms	1	1	100.00
		xbar_random_slow_rsp	11.220m	4.081ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	48.610s	91.874us	1	1	100.00
		xbar_error_and_unmapped_addr	35.020s	84.342us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.603m	302.448us	1	1	100.00
		xbar_error_and_unmapped_addr	35.020s	84.342us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	59.790s	65.766us	1	1	100.00
		xbar_access_same_device_slow_rsp	25.780m	9.574ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.065m	167.541us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	9.255m	467.042us	1	1	100.00
		xbar_stress_all_with_error	4.458m	310.366us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	20.792m	631.276us	1	1	100.00
		xbar_stress_all_with_reset_error	12.691m	1.363ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	11.640s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	13.988s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.867s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.118s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.747s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.845s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.587s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.781s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.781s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.498s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.151s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.878s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.901s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.002s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	13.396s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	13.130s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.017s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	13.920s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.581s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	13.016s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.865s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.456s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	13.179s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.957s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.059s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.159s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.885s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.666s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.231s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.408s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.388s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.928s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.636s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.880s		0	1	0.00
		rom_e2e_asm_init_dev	11.021s		0	1	0.00
		rom_e2e_asm_init_prod	11.122s		0	1	0.00
		rom_e2e_asm_init_prod_end	10.837s		0	1	0.00
		rom_e2e_asm_init_rma	11.400s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.872s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.493s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.746s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.744s		0	1	0.00
V2		TOTAL			64	205	31.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.432m	3.552ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.981m	4.936ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.475s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.051s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.432s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	13.415s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	19.756m	16.453ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	13.591s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	16.935m	11.925ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.438s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.958s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.475s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.051s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.432s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.127s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.852s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.562s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.157m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	21.047m	15.012ms	1	1	100.00
		chip_plic_all_irqs_0	8.934m	6.026ms	1	1	100.00
		chip_plic_all_irqs_10	8.973m	5.493ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.954m	6.079ms	1	1	100.00
		chip_sw_dma_abort	4.755m	5.020ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.524s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.522s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.309s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.902s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.901s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	12.185s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.379s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.183s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.532s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.898s		0	1	0.00
		chip_sw_mbx_smoketest	4.148m	4.164ms	1	1	100.00
		TOTAL			75	247	30.36

Failure Buckets

Job returned non-zero exit code has 141 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.42361521470990102542845219458055471234901833253856074844361411576995548317796
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (1a8cd3)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (48e53f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 77.062s, Critical Path: 0.04s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.96563245855418184185103518335839779071668964038785684799259456103860456415664
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (948f87)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 76.593s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.9934179756257333510216428673531235778839884148469529590250846453837833322418
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (62dc33)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 117.751s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.62617648056432653849287980426666316181532941938076013705813976419579784438823
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (6450e3)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 85.629s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.72169932609644282330111975497632295010438211424545707363787287252342135843539
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (ee681d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 78.045s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 136 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.16169692506119744958703913533647971892981796113279490375248317335247935375510
    Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.32507663742482408448930313018502078426442836146916908254133469736530206660113
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.81703975333897899467626894897667538793028295313884772866790011016603336219413
    Line 406, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.19940888833970724408815285428512875000498083361883088424454654894015333729353
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.56473627820042517238882064971908103397024316714450958294497453900551062657741
    Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_rstmgr_alert_info has 1 failures.

0.chip_sw_rstmgr_alert_info.72722169106311875199193437979367523901671338921402298011492774993746472253422
Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30016.160502 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30016.160502 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.12989286157777151530189816186039966892762742722647008569879407366310514757260
Line 465, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20017.025154 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20017.025154 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.99745898035173872153622631427605911805251523689548583263865822774673263903004
Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18017.468233 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.468233 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.40486288494938547303319557014063786566843232357051449196961837835544904017589
Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18021.436417 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18021.436417 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.50154319655914691782388522740530229883467970129078910759402012175659416711802
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.79391998851419040728889666351609030092322028965738052554385579083055931935312
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.36811146822711310228188082752914316442235327641402495659241790601475702648168
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.66452181104729379619234222240934831067269450117465818062303981118367526832634
Line 476, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8855.718702 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (101387998103394433961227773392861358287654347889401292697115347541005952470021 [0xe02792c5b5bf722fd3338cb174d12a65b44cab7d2e58fd0578436cfcbc39cc05] vs 66835582946529193297812598089298059819005923566198395000750418161554460230030 [0x93c39971801dc33397944781fc3bc8a9d28919b9575a37ffbae42396a24bc18e])
  UVM_INFO @ 8855.718702 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.37699376366287625829462939186913249954207290130666485784684558778829568337115
Line 474, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 6530.134360 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (77368440203615848247982274021895879484577456177900650374555733205579608575029 [0xab0cfc3eb933487f0a634ca1ae9ca73460731e09f591ea92c2b7f076d5734c35] vs 77728485430744816253453812512700409393893785148379231562791449090538729957632 [0xabd8c3826ef0dfc462fe1f08b5112085ec4ae62e8fa2a2d2786061f2e138e900])
  UVM_INFO @ 6530.134360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.50830079740964266423958479275552871369092412142051733929122347028769062951728
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4653.994745 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h4be56453  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'he  a_opcode: 'h1  a_user: 'h248f9  d_param: 'h0  d_source: 'he  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4653.994745 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.74583218600305886823128104506755354390650776605649653714509023973417018247109
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5207.790255 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'he8afd2df  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h0  a_user: 'h2696f  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5207.790255 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.109158374443480552829542106123391651732712009013343572232941675893827216404079
    Line 452, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3996.823748 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3996.823748 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_smoketest_sim_dv(sw/device/tests/soc_proxy_smoketest.c:34)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceTwo, kDifToggleEnabled) returns * has 1 failures:
- Test chip_sw_soc_proxy_smoketest has 1 failures.
  - 0.chip_sw_soc_proxy_smoketest.114939425186784339656373020690157226223570376020413096163393210592352067432612
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
```
  UVM_ERROR @ 5536.195090 us: (sw_logger_if.sv:526) [soc_proxy_smoketest_sim_dv(sw/device/tests/soc_proxy_smoketest.c:34)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceTwo, kDifToggleEnabled) returns 3
  UVM_INFO @ 5536.195090 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.14856545672207984260556602722435619558653281766790778787518985577567070594504
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5648.104560 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5648.104560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.29574954509092444648350470778172925181439848192235945208858352054658626741580
    Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4696.495424 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4696.495424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.19196581849270570005929616971044863670116315577655410116623983848184289476922
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5556.404930 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5556.404930 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.532130753992213498584549096035936486921120414269737253196671296988813533091
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5012.588806 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5012.588806 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.14705510311933424257895673435152438612672576809458103446937797570363910794605
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@35946) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.86465181357895380421079812793921990570936065798926513263652289732171685539768
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 4116.352700 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@35946) { a_addr: 'h1465210  a_data: 'h8ceb25a8  a_mask: 'ha  a_size: 'h2  a_param: 'h0  a_source: 'h2c  a_opcode: 'h4  a_user: 'h24314  d_param: 'h0  d_source: 'h2c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4116.352700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.36969992544422818464968174747489865691755154797240428933754505100105219689504
    Line 403, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13711.215192 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13711.215192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.97604401371736965477028653156281459049869536579074200010421037182908618226244
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.113270273161360574980884255741819821075087527959572853323334155510325195470561
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5019.965464 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5019.965464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```