DMA Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	417.174us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	7.000s	1.371ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	673.174us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	20.119us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	29.124us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	12.000s	4.130ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	652.906us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	229.377us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	29.124us	1	1	100.00
		dma_csr_aliasing	7.000s	652.906us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	31.000s	10.197ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	3.283m	13.988ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	4.833m	177.399ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	3.633m	43.376ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	3.283m	13.988ms	1	1	100.00
V2	dma_abort	dma_abort	18.000s	4.964ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.033m	19.625ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	47.143us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	101.737us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	101.737us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	20.119us	1	1	100.00
		dma_csr_rw	4.000s	29.124us	1	1	100.00
		dma_csr_aliasing	7.000s	652.906us	1	1	100.00
		dma_same_csr_outstanding	5.000s	115.354us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	20.119us	1	1	100.00
		dma_csr_rw	4.000s	29.124us	1	1	100.00
		dma_csr_aliasing	7.000s	652.906us	1	1	100.00
		dma_same_csr_outstanding	5.000s	115.354us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	24.000s	499.355us	1	1	100.00
		dma_generic_stress	3.633m	43.376ms	1	1	100.00
		dma_handshake_stress	3.283m	13.988ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	400.262us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.167m	30.560ms	1	1	100.00
		dma_longer_transfer	10.000s	1.728ms	1	1	100.00
		TOTAL			21	21	100.00