EDN Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.910s	31.036us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.650s	25.670us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.690s	39.597us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.580s	708.471us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.950s	18.209us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.700s	19.047us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.690s	39.597us	1	1	100.00
		edn_csr_aliasing	1.950s	18.209us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.810s	172.999us	1	1	100.00
V2	csrng_commands	edn_genbits	1.810s	172.999us	1	1	100.00
V2	genbits	edn_genbits	1.810s	172.999us	1	1	100.00
V2	interrupts	edn_intr	2.310s	23.439us	1	1	100.00
V2	alerts	edn_alert	1.870s	97.689us	1	1	100.00
V2	errs	edn_err	1.910s	32.515us	1	1	100.00
V2	disable	edn_disable	1.810s	13.263us	1	1	100.00
		edn_disable_auto_req_mode	1.820s	42.122us	1	1	100.00
V2	stress_all	edn_stress_all	4.720s	445.026us	1	1	100.00
V2	intr_test	edn_intr_test	1.770s	59.194us	1	1	100.00
V2	alert_test	edn_alert_test	1.630s	13.659us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.880s	444.454us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.880s	444.454us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.650s	25.670us	1	1	100.00
		edn_csr_rw	1.690s	39.597us	1	1	100.00
		edn_csr_aliasing	1.950s	18.209us	1	1	100.00
		edn_same_csr_outstanding	1.790s	25.687us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.650s	25.670us	1	1	100.00
		edn_csr_rw	1.690s	39.597us	1	1	100.00
		edn_csr_aliasing	1.950s	18.209us	1	1	100.00
		edn_same_csr_outstanding	1.790s	25.687us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.400s	461.373us	1	1	100.00
		edn_tl_intg_err	2.330s	52.330us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.870s	18.575us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.870s	97.689us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.400s	461.373us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.400s	461.373us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.400s	461.373us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.400s	461.373us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.870s	97.689us	1	1	100.00
		edn_sec_cm	6.400s	461.373us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.870s	97.689us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.330s	52.330us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	53.510s	8.854ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00