HMAC Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.760s 154.336us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.930s 21.362us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.840s 485.255us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.360s 2.617ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.760s 7.033ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.270s 46.717us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.840s 485.255us 1 1 100.00
hmac_csr_aliasing 6.760s 7.033ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 28.350s 9.135ms 1 1 100.00
V2 back_pressure hmac_back_pressure 44.760s 1.103ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.773m 6.313ms 1 1 100.00
hmac_test_sha384_vectors 19.600s 1.444ms 1 1 100.00
hmac_test_sha512_vectors 19.420s 230.636us 1 1 100.00
hmac_test_hmac256_vectors 9.290s 4.042ms 1 1 100.00
hmac_test_hmac384_vectors 11.130s 1.510ms 1 1 100.00
hmac_test_hmac512_vectors 11.330s 1.551ms 1 1 100.00
V2 burst_wr hmac_burst_wr 7.530s 998.048us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 26.880s 478.488us 1 1 100.00
V2 error hmac_error 12.490s 3.973ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.259m 29.305ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.760s 154.336us 1 1 100.00
hmac_long_msg 28.350s 9.135ms 1 1 100.00
hmac_back_pressure 44.760s 1.103ms 1 1 100.00
hmac_datapath_stress 26.880s 478.488us 1 1 100.00
hmac_burst_wr 7.530s 998.048us 1 1 100.00
hmac_stress_all 1.584m 9.924ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.760s 154.336us 1 1 100.00
hmac_long_msg 28.350s 9.135ms 1 1 100.00
hmac_back_pressure 44.760s 1.103ms 1 1 100.00
hmac_datapath_stress 26.880s 478.488us 1 1 100.00
hmac_wipe_secret 1.259m 29.305ms 1 1 100.00
hmac_test_sha256_vectors 2.773m 6.313ms 1 1 100.00
hmac_test_sha384_vectors 19.600s 1.444ms 1 1 100.00
hmac_test_sha512_vectors 19.420s 230.636us 1 1 100.00
hmac_test_hmac256_vectors 9.290s 4.042ms 1 1 100.00
hmac_test_hmac384_vectors 11.130s 1.510ms 1 1 100.00
hmac_test_hmac512_vectors 11.330s 1.551ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.760s 154.336us 1 1 100.00
hmac_long_msg 28.350s 9.135ms 1 1 100.00
hmac_back_pressure 44.760s 1.103ms 1 1 100.00
hmac_datapath_stress 26.880s 478.488us 1 1 100.00
hmac_burst_wr 7.530s 998.048us 1 1 100.00
hmac_error 12.490s 3.973ms 1 1 100.00
hmac_wipe_secret 1.259m 29.305ms 1 1 100.00
hmac_test_sha256_vectors 2.773m 6.313ms 1 1 100.00
hmac_test_sha384_vectors 19.600s 1.444ms 1 1 100.00
hmac_test_sha512_vectors 19.420s 230.636us 1 1 100.00
hmac_test_hmac256_vectors 9.290s 4.042ms 1 1 100.00
hmac_test_hmac384_vectors 11.130s 1.510ms 1 1 100.00
hmac_test_hmac512_vectors 11.330s 1.551ms 1 1 100.00
hmac_stress_all 1.584m 9.924ms 1 1 100.00
V2 stress_all hmac_stress_all 1.584m 9.924ms 1 1 100.00
V2 alert_test hmac_alert_test 1.610s 12.678us 1 1 100.00
V2 intr_test hmac_intr_test 1.610s 15.792us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.080s 26.535us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.080s 26.535us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.930s 21.362us 1 1 100.00
hmac_csr_rw 1.840s 485.255us 1 1 100.00
hmac_csr_aliasing 6.760s 7.033ms 1 1 100.00
hmac_same_csr_outstanding 2.080s 63.374us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.930s 21.362us 1 1 100.00
hmac_csr_rw 1.840s 485.255us 1 1 100.00
hmac_csr_aliasing 6.760s 7.033ms 1 1 100.00
hmac_same_csr_outstanding 2.080s 63.374us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.920s 560.636us 1 1 100.00
hmac_tl_intg_err 2.440s 191.027us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.440s 191.027us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.760s 154.336us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.350s 55.975us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 4.049m 4.091ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.900s 490.243us 1 1 100.00
TOTAL 28 28 100.00