I2C Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: `a29a8cc`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	26.690s	2.016ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.530s	8.700ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.740s	67.767us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.620s	20.330us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.910s	283.205us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.220s	139.899us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.720s	37.603us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.620s	20.330us	1	1	100.00
		i2c_csr_aliasing	2.220s	139.899us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.220s	782.210us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	18.051m	17.584ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	18.280s	4.357ms	1	1	100.00
V2	host_override	i2c_host_override	1.640s	17.287us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.492m	6.498ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	25.240s	6.674ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.570s	62.914us	1	1	100.00
		i2c_host_fifo_fmt_empty	9.630s	524.896us	1	1	100.00
		i2c_host_fifo_reset_rx	2.960s	143.581us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	46.230s	6.437ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.130s	837.573us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.550s	126.625us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.080s	2.693ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	4.576m	29.266ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.080s	2.891ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	44.490s	1.420ms	1	1	100.00
		i2c_target_intr_smoke	3.770s	2.519ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.250s	297.648us	1	1	100.00
		i2c_target_fifo_reset_tx	2.120s	684.086us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	28.800s	32.771ms	1	1	100.00
		i2c_target_stress_rd	44.490s	1.420ms	1	1	100.00
		i2c_target_intr_stress_wr	26.550s	13.693ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.350s	2.646ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	45.480s	3.259ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.740s	4.062ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.660s	1.051ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.310s	374.119us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.820s	403.345us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	18.280s	4.357ms	1	1	100.00
		i2c_host_perf_precise	6.940s	652.814us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.130s	837.573us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.360s	92.383us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.940s	1.051ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.640s	492.932us	1	1	100.00
		i2c_target_nack_txstretch	1.980s	519.299us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.600s	577.673us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.420s	2.002ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.470s	46.022us	1	1	100.00
V2	intr_test	i2c_intr_test	1.670s	30.891us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.390s	101.111us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.390s	101.111us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.740s	67.767us	1	1	100.00
		i2c_csr_rw	1.620s	20.330us	1	1	100.00
		i2c_csr_aliasing	2.220s	139.899us	1	1	100.00
		i2c_same_csr_outstanding	1.540s	35.565us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.740s	67.767us	1	1	100.00
		i2c_csr_rw	1.620s	20.330us	1	1	100.00
		i2c_csr_aliasing	2.220s	139.899us	1	1	100.00
		i2c_same_csr_outstanding	1.540s	35.565us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.160s	56.553us	1	1	100.00
		i2c_sec_cm	1.680s	40.957us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.160s	56.553us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	25.140s	774.460us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.680s	1.974ms	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	4.200s	232.475us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.28642177379761789416123634336836010661091098244114306782633040532552272052564
Line 157, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 17584485666 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @13126712

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.81429352367160107338768097212600504874670150474568346401582389546311031648558
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 126625496 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @26523

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.67320023723842262349215719484270796109484430445563205819608652106143939546419
    Line 89, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 774460401 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 774460401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.77954702916262954016470001314518286968647553704806014471148633842291472534574
    Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 232475203 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 232475203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.91462774408348623836665678729181136906413674320042698675572966940550339236093
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 1973617072 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 1973617072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```