KEYMGR Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.140s	241.220us	1	1	100.00
V1	random	keymgr_random	3.890s	118.157us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.200s	34.932us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.950s	66.059us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	3.230s	899.136us	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	3.000s	346.012us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.430s	52.785us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.950s	66.059us	1	1	100.00
		keymgr_csr_aliasing	3.000s	346.012us	0	1	0.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	3.520s	322.889us	1	1	100.00
V2	sideload	keymgr_sideload	4.070s	536.027us	1	1	100.00
		keymgr_sideload_kmac	3.340s	67.108us	1	1	100.00
		keymgr_sideload_aes	3.240s	68.500us	1	1	100.00
		keymgr_sideload_otbn	2.570s	121.642us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.740s	29.157us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.720s	234.804us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.050s	76.997us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	20.270s	889.223us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.720s	170.299us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.520s	304.523us	1	1	100.00
V2	stress_all	keymgr_stress_all	53.060s	3.646ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.760s	42.943us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.640s	19.247us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.930s	681.222us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.930s	681.222us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.200s	34.932us	1	1	100.00
		keymgr_csr_rw	1.950s	66.059us	1	1	100.00
		keymgr_csr_aliasing	3.000s	346.012us	0	1	0.00
		keymgr_same_csr_outstanding	2.620s	215.031us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.200s	34.932us	1	1	100.00
		keymgr_csr_rw	1.950s	66.059us	1	1	100.00
		keymgr_csr_aliasing	3.000s	346.012us	0	1	0.00
		keymgr_same_csr_outstanding	2.620s	215.031us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	6.430s	1.079ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.430s	1.079ms	1	1	100.00
		keymgr_tl_intg_err	1.670s	47.066us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.180s	329.996us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.180s	329.996us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.180s	329.996us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.180s	329.996us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	2.360s	230.635us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	6.430s	1.079ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.430s	1.079ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.670s	47.066us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.180s	329.996us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.520s	322.889us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.890s	118.157us	1	1	100.00
		keymgr_csr_rw	1.950s	66.059us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.890s	118.157us	1	1	100.00
		keymgr_csr_rw	1.950s	66.059us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.890s	118.157us	1	1	100.00
		keymgr_csr_rw	1.950s	66.059us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.720s	234.804us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.720s	170.299us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.720s	170.299us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.890s	118.157us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.860s	139.126us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.430s	1.079ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.430s	1.079ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.430s	1.079ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	5.930s	266.878us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.720s	234.804us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.430s	1.079ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.430s	1.079ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.430s	1.079ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	5.930s	266.878us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	5.930s	266.878us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.430s	1.079ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	5.930s	266.878us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.430s	1.079ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	5.930s	266.878us	1	1	100.00
V2S		TOTAL			4	6	66.67
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	7.810s	577.425us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	30	86.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 4 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.101819591394145247187289200794501688968008762818804761479447267180987301837497
      Line 82, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
        UVM_ERROR @ 230635050 ps: (keymgr_csr_assert_fpv.sv:466) [ASSERT FAILED] attest_sw_binding_7_rd_A
        UVM_INFO @ 230635050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.58683923264758016954084096973543729798703253320194770084555932203185648808232
      Line 82, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
        UVM_ERROR @  47066487 ps: (keymgr_csr_assert_fpv.sv:411) [ASSERT FAILED] sealing_sw_binding_4_rd_A
        UVM_INFO @  47066487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.10166106656829933378829723015418684440899524586452363036504462089895433664455
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
        UVM_ERROR @ 899136313 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
        UVM_INFO @ 899136313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_aliasing has 1 failures.

    • 0.keymgr_csr_aliasing.30621629341016388029899306522502689626085543191520570226031679289656343518292
      Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
        UVM_ERROR @ 346011522 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
        UVM_INFO @ 346011522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---