KMAC/MASKED Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	25.500s	24.762ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.650s	60.920us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.730s	22.900us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.480s	987.149us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.960s	282.843us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.710s	142.886us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.730s	22.900us	1	1	100.00
		kmac_csr_aliasing	5.960s	282.843us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.630s	20.909us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.210s	44.461us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	30.302m	23.296ms	1	1	100.00
V2	burst_write	kmac_burst_write	11.265m	8.957ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.525m	276.259ms	1	1	100.00
		kmac_test_vectors_sha3_256	27.740s	1.223ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.980s	7.403ms	1	1	100.00
		kmac_test_vectors_sha3_512	16.310s	758.627us	1	1	100.00
		kmac_test_vectors_shake_128	25.855m	20.564ms	1	1	100.00
		kmac_test_vectors_shake_256	4.800m	36.802ms	1	1	100.00
		kmac_test_vectors_kmac	3.480s	115.271us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.310s	64.998us	1	1	100.00
V2	sideload	kmac_sideload	1.095m	14.403ms	1	1	100.00
V2	app	kmac_app	2.039m	24.074ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.781m	29.094ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	11.530s	2.246ms	1	1	100.00
V2	error	kmac_error	30.680s	6.595ms	1	1	100.00
V2	key_error	kmac_key_error	14.390s	14.336ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.550s	178.831us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	17.280s	264.883us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.250s	178.852us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	30.130s	15.305ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.340s	135.058us	1	1	100.00
V2	stress_all	kmac_stress_all	11.707m	47.132ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.640s	18.870us	1	1	100.00
V2	alert_test	kmac_alert_test	1.750s	15.659us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.920s	170.535us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.920s	170.535us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.650s	60.920us	1	1	100.00
		kmac_csr_rw	1.730s	22.900us	1	1	100.00
		kmac_csr_aliasing	5.960s	282.843us	1	1	100.00
		kmac_same_csr_outstanding	2.790s	46.658us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.650s	60.920us	1	1	100.00
		kmac_csr_rw	1.730s	22.900us	1	1	100.00
		kmac_csr_aliasing	5.960s	282.843us	1	1	100.00
		kmac_same_csr_outstanding	2.790s	46.658us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.940s	490.040us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.940s	490.040us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.940s	490.040us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.940s	490.040us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.220s	763.523us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	39.030s	4.378ms	1	1	100.00
		kmac_tl_intg_err	3.670s	102.869us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.670s	102.869us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.340s	135.058us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	25.500s	24.762ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.095m	14.403ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.940s	490.040us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	39.030s	4.378ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	39.030s	4.378ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	39.030s	4.378ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	25.500s	24.762ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.340s	135.058us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	39.030s	4.378ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.035m	33.000ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	25.500s	24.762ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	47.620s	4.017ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.52923939951911891263377232446721893086054009577433352134502384022700089081108
      Line 153, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4017117232 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 4017117232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---