KMAC/UNMASKED Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	27.840s	8.522ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.010s	39.534us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.800s	33.967us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	8.510s	1.496ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.250s	134.396us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.210s	87.120us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.800s	33.967us	1	1	100.00
		kmac_csr_aliasing	4.250s	134.396us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.970s	16.221us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.960s	36.723us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	20.163m	206.129ms	1	1	100.00
V2	burst_write	kmac_burst_write	14.570s	220.390us	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	22.255m	129.239ms	1	1	100.00
		kmac_test_vectors_sha3_256	25.690s	1.617ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.950s	2.463ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.896m	80.362ms	1	1	100.00
		kmac_test_vectors_shake_128	1.901m	14.963ms	1	1	100.00
		kmac_test_vectors_shake_256	1.396m	4.968ms	1	1	100.00
		kmac_test_vectors_kmac	2.570s	38.534us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.900s	61.218us	1	1	100.00
V2	sideload	kmac_sideload	3.717m	8.127ms	1	1	100.00
V2	app	kmac_app	23.080s	7.368ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.069m	7.109ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.497m	12.297ms	1	1	100.00
V2	error	kmac_error	50.150s	4.139ms	1	1	100.00
V2	key_error	kmac_key_error	3.260s	605.311us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.720s	82.306us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	13.020s	2.643ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	17.270s	8.809ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	5.340s	388.429us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.350s	51.396us	1	1	100.00
V2	stress_all	kmac_stress_all	18.790s	2.384ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.840s	18.789us	1	1	100.00
V2	alert_test	kmac_alert_test	1.680s	15.166us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.600s	230.030us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.600s	230.030us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.010s	39.534us	1	1	100.00
		kmac_csr_rw	1.800s	33.967us	1	1	100.00
		kmac_csr_aliasing	4.250s	134.396us	1	1	100.00
		kmac_same_csr_outstanding	2.250s	75.291us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.010s	39.534us	1	1	100.00
		kmac_csr_rw	1.800s	33.967us	1	1	100.00
		kmac_csr_aliasing	4.250s	134.396us	1	1	100.00
		kmac_same_csr_outstanding	2.250s	75.291us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.330s	99.913us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.330s	99.913us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.330s	99.913us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.330s	99.913us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.020s	119.805us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	27.830s	9.021ms	1	1	100.00
		kmac_tl_intg_err	4.350s	762.766us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.350s	762.766us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.350s	51.396us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	27.840s	8.522ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.717m	8.127ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.330s	99.913us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	27.830s	9.021ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	27.830s	9.021ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	27.830s	9.021ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	27.840s	8.522ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.350s	51.396us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	27.830s	9.021ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.901m	42.250ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	27.840s	8.522ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.463m	8.396ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.77841995692837547014353268286310809526259709410586809209611337791365572553081
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
        UVM_ERROR @ 119805109 ps: (kmac_csr_assert_fpv.sv:522) [ASSERT FAILED] prefix_6_rd_A
        UVM_INFO @ 119805109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---