a29a8cc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 36.000s | 14.165ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 19.319us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 12.465us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 378.541us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 24.088us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 3.561us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 12.465us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 24.088us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 48.000s | 3.549ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 15.000s | 117.364us | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 1.233m | 17.003ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 8.000s | 45.773us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 7.000s | 4.008us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 7.000s | 4.008us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 19.319us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 12.465us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 24.088us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 24.121us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 19.319us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 12.465us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 24.088us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 24.121us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 9.000s | 35.088us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 6.000s | 54.134us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 2 failures:
Test mbx_tl_errors has 1 failures.
0.mbx_tl_errors.64405859296438578008616957320610114914943158144610778241431337355505348834852
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 4007785 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x7514b80b a_data = 0xeec7823b a_mask = 0x4 a_size = 0x0 a_param = 0x0 a_source = 0x9a a_opcode = PutPartialData a_user = 0x2422c d_data = 0xd6ff3b4c d_size = 0x3 d_param = 0x0 d_source = 0x60 d_opcode = AccessAckData d_error = 0 d_user = 10110000101010 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 4007785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_tl_intg_err has 1 failures.
0.mbx_tl_intg_err.63584912708963743068024863644570928374619069218615238176681572421580145230559
Line 88, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 54133612 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x6b9a675a a_data = 0x183ae59f a_mask = 0x4 a_size = 0x1 a_param = 0x0 a_source = 0xd4 a_opcode = PutPartialData a_user = 0x26545 d_data = 0x408a0291 d_size = 0x2 d_param = 0x0 d_source = 0x98 d_opcode = AccessAckData d_error = 0 d_user = 1000000110011 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 54133612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.13827140184920492100219016126147925718063967438610926327567018385112567894606
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 3561197 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xded79ace a_data = 0xae667fb9 a_mask = 0x0 a_size = 0x3 a_param = 0x0 a_source = 0xc0 a_opcode = Get a_user = 0x27c8c d_data = 0xa315a6a2 d_size = 0x3 d_param = 0x0 d_source = 0xf9 d_opcode = AccessAck d_error = 0 d_user = 11011111000101 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 3561197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---