OTBN Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	239.978us	1	1	100.00
V1	single_binary	otbn_single	8.000s	24.132us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	139.886us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	40.930us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	521.909us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	36.854us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	197.907us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	40.930us	1	1	100.00
		otbn_csr_aliasing	6.000s	36.854us	1	1	100.00
V1	mem_walk	otbn_mem_walk	22.000s	1.333ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	11.000s	209.074us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	33.000s	175.947us	1	1	100.00
V2	multi_error	otbn_multi_err	38.000s	416.665us	1	1	100.00
V2	back_to_back	otbn_multi	25.000s	768.827us	1	1	100.00
V2	stress_all	otbn_stress_all	51.000s	855.835us	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	32.664us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	24.372us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	11.000s	24.129us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	12.826us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	12.151us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	50.640us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	50.640us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	139.886us	1	1	100.00
		otbn_csr_rw	6.000s	40.930us	1	1	100.00
		otbn_csr_aliasing	6.000s	36.854us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	15.139us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	139.886us	1	1	100.00
		otbn_csr_rw	6.000s	40.930us	1	1	100.00
		otbn_csr_aliasing	6.000s	36.854us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	15.139us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	11.000s	25.936us	1	1	100.00
		otbn_dmem_err	9.000s	49.472us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	8.000s	13.938us	1	1	100.00
		otbn_controller_ispr_rdata_err	10.000s	146.362us	1	1	100.00
		otbn_mac_bignum_acc_err	11.000s	77.400us	1	1	100.00
		otbn_urnd_err	6.000s	25.089us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	17.079us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	20.881us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	6.000s	50.098us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	12.000s	34.387us	0	1	0.00
		otbn_tl_intg_err	20.000s	116.865us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	25.000s	327.383us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	12.000s	34.387us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	12.000s	34.387us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	239.978us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	9.000s	49.472us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	25.936us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	20.000s	116.865us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	32.664us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	25.936us	1	1	100.00
		otbn_dmem_err	9.000s	49.472us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	24.372us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	17.079us	1	1	100.00
		otbn_sec_cm	12.000s	34.387us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	12.000s	34.387us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	8.000s	24.132us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	25.936us	1	1	100.00
		otbn_dmem_err	9.000s	49.472us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	24.372us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	17.079us	1	1	100.00
		otbn_sec_cm	12.000s	34.387us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	12.000s	34.387us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	32.664us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	25.936us	1	1	100.00
		otbn_dmem_err	9.000s	49.472us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	24.372us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	17.079us	1	1	100.00
		otbn_sec_cm	12.000s	34.387us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	12.000s	34.387us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	8.000s	24.132us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	100.347us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	7.000s	98.401us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	20.000s	236.239us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	20.000s	236.239us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	55.594us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	12.000s	34.387us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	12.000s	34.387us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	9.000s	56.343us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	12.000s	34.387us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	12.000s	34.387us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	79.518us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	79.518us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	12.000s	52.446us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	8.000s	24.132us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	8.000s	24.132us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	8.000s	24.132us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	25.000s	768.827us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	8.000s	24.132us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	8.000s	24.132us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	8.000s	215.135us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	8.000s	24.132us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	12.000s	34.387us	0	1	0.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	2.517m	2.011ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Failure Buckets

• UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.40103149007522812680332455189998958819098103270599148407305316953416344418033
      Line 162, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 2010901183 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 2010901183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.53225597486993036238692676019676909408068595983774951895665603277157486261674
      Line 114, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 34386940 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 34386940 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  34386940 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  34386940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---