ROM_CTRL/32KB Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.420s 312.781us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 4.370s 1.242ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.570s 556.660us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.250s 1.073ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.920s 660.683us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 3.940s 1.265ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.570s 556.660us 1 1 100.00
rom_ctrl_csr_aliasing 4.920s 660.683us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 3.660s 386.749us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.760s 660.042us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.580s 187.481us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 13.710s 1.503ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 10.140s 300.642us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.360s 661.332us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.150s 203.085us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.150s 203.085us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 4.370s 1.242ms 1 1 100.00
rom_ctrl_csr_rw 4.570s 556.660us 1 1 100.00
rom_ctrl_csr_aliasing 4.920s 660.683us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.250s 170.251us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 4.370s 1.242ms 1 1 100.00
rom_ctrl_csr_rw 4.570s 556.660us 1 1 100.00
rom_ctrl_csr_aliasing 4.920s 660.683us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.250s 170.251us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 22.780s 3.437ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.993m 3.336ms 1 1 100.00
rom_ctrl_tl_intg_err 27.740s 577.365us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.993m 3.336ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.993m 3.336ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.993m 3.336ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.993m 3.336ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.420s 312.781us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.420s 312.781us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.420s 312.781us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 27.740s 577.365us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_kmac_err_chk 10.140s 300.642us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 22.780s 3.437ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.993m 3.336ms 1 1 100.00
V2S TOTAL 3 4 75.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.603m 2.421ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 18 19 94.74

Failure Buckets