ROM_CTRL/64KB Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.290s 311.920us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.140s 1.426ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.550s 791.857us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.840s 291.968us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.560s 297.554us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 9.420s 772.075us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.550s 791.857us 1 1 100.00
rom_ctrl_csr_aliasing 7.560s 297.554us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.690s 699.697us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 9.430s 376.657us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.300s 608.854us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 29.560s 1.266ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.540s 3.714ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.440s 294.086us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.030s 206.989us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.030s 206.989us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.140s 1.426ms 1 1 100.00
rom_ctrl_csr_rw 6.550s 791.857us 1 1 100.00
rom_ctrl_csr_aliasing 7.560s 297.554us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.320s 1.067ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.140s 1.426ms 1 1 100.00
rom_ctrl_csr_rw 6.550s 791.857us 1 1 100.00
rom_ctrl_csr_aliasing 7.560s 297.554us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.320s 1.067ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 25.270s 2.771ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.555m 1.751ms 1 1 100.00
rom_ctrl_tl_intg_err 1.151m 443.473us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.555m 1.751ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.555m 1.751ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.555m 1.751ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.555m 1.751ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.290s 311.920us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.290s 311.920us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.290s 311.920us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.151m 443.473us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_kmac_err_chk 11.540s 3.714ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 25.270s 2.771ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.555m 1.751ms 1 1 100.00
V2S TOTAL 3 4 75.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.115m 6.577ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 18 19 94.74

Failure Buckets