RV_TIMER Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.690s	12.200us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.560s	18.167us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.640s	23.232us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.210s	574.600us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.710s	28.239us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.780s	60.732us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.640s	23.232us	1	1	100.00
		rv_timer_csr_aliasing	1.710s	28.239us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	10.560s	20.556ms	1	1	100.00
V2	disabled	rv_timer_disabled	1.530s	67.441us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	4.942m	568.812ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	4.942m	568.812ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.630s	20.646us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.540s	27.565us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.540s	45.281us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.040s	164.842us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.040s	164.842us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.560s	18.167us	1	1	100.00
		rv_timer_csr_rw	1.640s	23.232us	1	1	100.00
		rv_timer_csr_aliasing	1.710s	28.239us	1	1	100.00
		rv_timer_same_csr_outstanding	1.700s	18.732us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.560s	18.167us	1	1	100.00
		rv_timer_csr_rw	1.640s	23.232us	1	1	100.00
		rv_timer_csr_aliasing	1.710s	28.239us	1	1	100.00
		rv_timer_same_csr_outstanding	1.700s	18.732us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.820s	175.951us	1	1	100.00
		rv_timer_tl_intg_err	2.200s	460.007us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.200s	460.007us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	18.470s	6.698ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.330s	41.874us	1	1	100.00
		rv_timer_max	1.640s	11.762us	1	1	100.00
		TOTAL			19	19	100.00