SPI_DEVICE/1R1W Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	40.910s	13.337ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.170s	23.181us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	3.120s	88.516us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	10.150s	1.722ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.910s	1.714ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.550s	464.506us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.120s	88.516us	1	1	100.00
		spi_device_csr_aliasing	14.910s	1.714ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.610s	17.799us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.160s	20.856us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.810s	56.318us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.930s	1.474us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.750s	5.382us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.380s	323.334us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.380s	323.334us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	6.850s	2.313ms	1	1	100.00
		spi_device_tpm_sts_read	1.980s	83.795us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	17.990s	3.149ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.860s	37.666us	1	1	100.00
		spi_device_flash_all	1.602m	63.411ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	6.520s	4.348ms	1	1	100.00
		spi_device_flash_all	1.602m	63.411ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	6.520s	4.348ms	1	1	100.00
		spi_device_flash_all	1.602m	63.411ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.602m	63.411ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.370s	97.561us	1	1	100.00
		spi_device_flash_all	1.602m	63.411ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.370s	97.561us	1	1	100.00
		spi_device_flash_all	1.602m	63.411ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.370s	97.561us	1	1	100.00
		spi_device_flash_all	1.602m	63.411ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.370s	97.561us	1	1	100.00
		spi_device_flash_all	1.602m	63.411ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.370s	97.561us	1	1	100.00
		spi_device_flash_all	1.602m	63.411ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.690s	74.731us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	10.700s	1.601ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	10.700s	1.601ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	10.700s	1.601ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	26.420s	2.790ms	1	1	100.00
		spi_device_read_buffer_direct	7.180s	4.750ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	10.700s	1.601ms	1	1	100.00
		spi_device_flash_all	1.602m	63.411ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.602m	63.411ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.602m	63.411ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.310s	111.285us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.310s	111.285us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	40.910s	13.337ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.105m	7.683ms	1	1	100.00
V2	stress_all	spi_device_stress_all	43.900s	51.269ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.630s	14.198us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.680s	25.112us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.650s	145.395us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.650s	145.395us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.170s	23.181us	1	1	100.00
		spi_device_csr_rw	3.120s	88.516us	1	1	100.00
		spi_device_csr_aliasing	14.910s	1.714ms	1	1	100.00
		spi_device_same_csr_outstanding	3.880s	44.253us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.170s	23.181us	1	1	100.00
		spi_device_csr_rw	3.120s	88.516us	1	1	100.00
		spi_device_csr_aliasing	14.910s	1.714ms	1	1	100.00
		spi_device_same_csr_outstanding	3.880s	44.253us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.870s	460.741us	1	1	100.00
		spi_device_tl_intg_err	6.720s	302.530us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.720s	302.530us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	11.550s	1.653ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.93259389721338366555741260074063431202864129140368765968008502211431603591338
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1101771 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[48])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1101771 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1101771 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[944])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.8887551013858312030237582216302357469430465521732657618317490089944251584439
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4631298 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4631298 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   4635298 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9092e6 [100100001001001011100110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   4635298 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x9092e6 [100100001001001011100110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])