SRAM_CTRL/MAIN Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	6.520s	461.718us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.500s	35.666us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.650s	42.327us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.580s	1.004ms	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.740s	14.197us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.040s	695.946us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.650s	42.327us	1	1	100.00
		sram_ctrl_csr_aliasing	1.740s	14.197us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.006m	18.761ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.004m	5.367ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.198m	10.803ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.573m	5.688ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	27.245m	67.571ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.902m	12.269ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	15.770s	3.347ms	1	1	100.00
V2	executable	sram_ctrl_executable	12.717m	131.422ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.390s	820.411us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.317m	54.151ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	10.070s	756.395us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	44.730s	1.568ms	1	1	100.00
		sram_ctrl_throughput_w_readback	44.460s	9.815ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.567m	21.473ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.980s	1.467ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	19.807m	119.132ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.480s	20.455us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.640s	32.685us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.640s	32.685us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.500s	35.666us	1	1	100.00
		sram_ctrl_csr_rw	1.650s	42.327us	1	1	100.00
		sram_ctrl_csr_aliasing	1.740s	14.197us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	25.604us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.500s	35.666us	1	1	100.00
		sram_ctrl_csr_rw	1.650s	42.327us	1	1	100.00
		sram_ctrl_csr_aliasing	1.740s	14.197us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	25.604us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	19.780s	7.242ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.630s	8.853us	0	1	0.00
		sram_ctrl_tl_intg_err	2.220s	195.987us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.630s	8.853us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.220s	195.987us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.567m	21.473ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.567m	21.473ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.650s	42.327us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	12.717m	131.422ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	12.717m	131.422ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	12.717m	131.422ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	15.770s	3.347ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.310s	719.900us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	19.780s	7.242ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.420s	675.665us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	6.520s	461.718us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	6.520s	461.718us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	12.717m	131.422ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.630s	8.853us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	15.770s	3.347ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.630s	8.853us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.630s	8.853us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	6.520s	461.718us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.630s	8.853us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	16.540s	3.714ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.104162445679097443587205505013463456109709824745204191362204163987588031895570
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 675664908 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x2d) != exp (0x9)
        UVM_INFO @ 675664908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.107190268381591768162101543740788251424466817738965794293764701956274972242329
      Line 102, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8852859 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8852859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---