SRAM_CTRL/RET Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.540s	626.773us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.740s	62.091us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.550s	14.532us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.200s	517.382us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.770s	53.994us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.410s	95.783us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.550s	14.532us	1	1	100.00
		sram_ctrl_csr_aliasing	1.770s	53.994us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.460s	1.602ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.150s	493.338us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	4.613m	4.220ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.462m	15.579ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	49.020s	6.050ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	10.604m	3.536ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	8.370s	866.802us	1	1	100.00
V2	executable	sram_ctrl_executable	7.761m	2.879ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	11.810s	296.410us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.261m	3.669ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	6.680s	131.905us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	18.820s	111.823us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.198m	289.655us	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.103m	31.954ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.680s	285.345us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	17.972m	40.340ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.880s	44.105us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.200s	112.973us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.200s	112.973us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.740s	62.091us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	14.532us	1	1	100.00
		sram_ctrl_csr_aliasing	1.770s	53.994us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.780s	62.905us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.740s	62.091us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	14.532us	1	1	100.00
		sram_ctrl_csr_aliasing	1.770s	53.994us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.780s	62.905us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.690s	1.537ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.550s	7.288us	0	1	0.00
		sram_ctrl_tl_intg_err	2.440s	484.941us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.550s	7.288us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.440s	484.941us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.103m	31.954ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.103m	31.954ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.550s	14.532us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.761m	2.879ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.761m	2.879ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.761m	2.879ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	8.370s	866.802us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.270s	98.942us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.690s	1.537ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.180s	43.616us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.540s	626.773us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.540s	626.773us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.761m	2.879ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.550s	7.288us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	8.370s	866.802us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.550s	7.288us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.550s	7.288us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.540s	626.773us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.550s	7.288us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	11.320s	1.706ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.9428677281709387474084925812931600703063222775387965487364121899780050166454
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7287617 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7287617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.21534242301912860220916509089672717823570339383187673468743429153789416000770
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  95783058 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (15 [0xf] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @  95783058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---