UART Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	23.340s	10.595ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.620s	17.287us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.590s	91.217us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.860s	499.756us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.620s	20.505us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.370s	120.454us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.590s	91.217us	1	1	100.00
		uart_csr_aliasing	1.620s	20.505us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	4.115m	157.930ms	1	1	100.00
V2	parity	uart_smoke	23.340s	10.595ms	1	1	100.00
		uart_tx_rx	4.115m	157.930ms	1	1	100.00
V2	parity_error	uart_intr	2.890s	5.661ms	1	1	100.00
		uart_rx_parity_err	2.549m	208.812ms	1	1	100.00
V2	watermark	uart_tx_rx	4.115m	157.930ms	1	1	100.00
		uart_intr	2.890s	5.661ms	1	1	100.00
V2	fifo_full	uart_fifo_full	16.040s	14.740ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	29.650s	21.702ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	8.680s	11.791ms	1	1	100.00
V2	rx_frame_err	uart_intr	2.890s	5.661ms	1	1	100.00
V2	rx_break_err	uart_intr	2.890s	5.661ms	1	1	100.00
V2	rx_timeout	uart_intr	2.890s	5.661ms	1	1	100.00
V2	perf	uart_perf	3.862m	27.666ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.100s	2.783ms	1	1	100.00
V2	line_loopback	uart_loopback	3.100s	2.783ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.119m	209.728ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.700s	644.861us	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.340s	2.360ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	3.430s	6.052ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	9.890m	105.033ms	1	1	100.00
V2	stress_all	uart_stress_all	2.054m	309.189ms	1	1	100.00
V2	alert_test	uart_alert_test	1.410s	12.888us	1	1	100.00
V2	intr_test	uart_intr_test	1.580s	54.055us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.210s	80.832us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.210s	80.832us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.620s	17.287us	1	1	100.00
		uart_csr_rw	1.590s	91.217us	1	1	100.00
		uart_csr_aliasing	1.620s	20.505us	1	1	100.00
		uart_same_csr_outstanding	1.480s	34.175us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.620s	17.287us	1	1	100.00
		uart_csr_rw	1.590s	91.217us	1	1	100.00
		uart_csr_aliasing	1.620s	20.505us	1	1	100.00
		uart_same_csr_outstanding	1.480s	34.175us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.460s	39.331us	1	1	100.00
		uart_tl_intg_err	2.020s	386.237us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.020s	386.237us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	17.550s	14.218ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00