CHIP Simulation Results

Thursday May 01 2025 17:06:40 UTC

GitHub Revision: `a29a8cc`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	8.610m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	8.610m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	8.175m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	8.590m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	7.753m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.827m	4.497ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.827m	4.497ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.827m	4.497ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	9.190m		0	1	0.00
		chip_sw_example_manufacturer	9.054m		0	1	0.00
		chip_sw_example_concurrency	4.389m	4.985ms	1	1	100.00
		chip_sw_uart_smoketest_signed	14.714s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	13.290s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	12.610s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	12.610s		0	1	0.00
V1	xbar_smoke	xbar_smoke	19.670s	63.297us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	8.333m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.063m	6.592ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.262m	5.043ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.619m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	7.215m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.425m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	7.831m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.530s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.530s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	9.193m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	8.772m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	8.790m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	8.790m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.630m	3.820ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.907m	3.422ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.985m	14.783ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.207s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.378s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.110m	18.318ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.674m	5.218ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	20.990m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	20.990m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.640s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.753m	4.772ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.753m	4.772ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.516m	18.024ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.392m	5.991ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.901m	3.337ms	1	1	100.00
		chip_sw_aes_idle	4.951m	5.895ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.509m	4.291ms	1	1	100.00
		chip_sw_kmac_idle	4.064m	4.238ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.469s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.474s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.325s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.548s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.484s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.592s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.608s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.541s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.440s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.898s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.042s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.484s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.592s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.608s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.541s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.440s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.898s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.042s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.527s		0	1	0.00
		chip_sw_aes_enc_jitter_en	45.670s	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.950s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.510s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	47.810s	10.180us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.080s		0	1	0.00
		chip_sw_clkmgr_jitter	4.135m	4.508ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.599m	5.611ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	18.900s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	46.460s	10.160us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	46.310s	10.100us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	45.590s	10.380us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	53.420s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	47.370s	10.400us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.254s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.951s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.705s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.577s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	16.259m	14.004ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.797m	15.769ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.753m	4.772ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	12.704s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.797m	15.769ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	25.590s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	19.587s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	25.678s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	14.564s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	1.070m		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	16.259m	14.004ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.985m	14.783ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	19.380m	20.017ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.563m	10.434ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.450m	30.017ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.664m	4.813ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	16.259m	14.004ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	13.135s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.554s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	16.259m	14.004ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.575s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.450m	30.017ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.631s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.546s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.362s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.366s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.594s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.605s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.554s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	23.585s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	4.589m		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	23.585s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	23.585s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	23.585s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.633m	9.557ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.314m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	3.696m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	3.472m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	2.695m		0	1	0.00
		chip_sw_lc_ctrl_transition	23.585s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.264m	8.021ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.821m	14.948ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.339s		0	1	0.00
		chip_prim_tl_access	2.331m	3.764ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.484s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.592s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.608s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.541s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.440s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.898s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.042s		0	1	0.00
		chip_rv_dm_lc_disabled	10.110m	18.318ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.243m	3.869ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	45.670s	10.300us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.288m	4.386ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.951m	5.895ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.748m	5.152ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	46.950s	10.340us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.509m	4.291ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.089m	4.468ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.531m	5.590ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	47.810s	10.180us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.264m	8.021ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	23.585s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	40.470s	10.220us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.277m	6.364ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.064m	4.238ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	10.456s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	10.456s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	11.394s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.831m	4.557ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	16.583s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.264m	8.021ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.510s	10.100us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	1.266m		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	18.527s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.901m	3.337ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.901m	3.337ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.901m	3.337ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.525m	5.602ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.821m	14.948ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.821m	14.948ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.192m	9.701ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.080s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.339s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	16.259m	14.004ms	1	1	100.00
		chip_sw_data_integrity_escalation	8.790m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	23.585s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.525m	5.602ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.264m	8.021ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.192m	9.701ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.891m	4.052ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.525m	5.602ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.264m	8.021ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.192m	9.701ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.891m	4.052ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	23.585s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.704s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	4.589m		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.314m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	3.696m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	3.472m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	2.695m		0	1	0.00
		chip_sw_lc_ctrl_transition	23.585s		0	1	0.00
		chip_prim_tl_access	2.331m	3.764ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.331m	3.764ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	38.263s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	2.218m		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.951s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.527s		0	1	0.00
		chip_sw_aes_enc_jitter_en	45.670s	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.950s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.510s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	47.810s	10.180us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.080s		0	1	0.00
		chip_sw_clkmgr_jitter	4.135m	4.508ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	4.578m	4.673ms	0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	4.578m	4.673ms	0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.917m	4.745ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.881m	3.767ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.288m	5.920ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.255m	5.189ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.918m	4.088ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.266m	4.207ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.891m	4.052ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	19.380m	20.017ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	19.380m	20.017ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.507m	4.036ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.690m	3.997ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.872m	3.996ms	1	1	100.00
		chip_sw_csrng_smoketest	3.187m	5.248ms	1	1	100.00
		chip_sw_gpio_smoketest	3.579m	3.744ms	1	1	100.00
		chip_sw_hmac_smoketest	3.828m	3.602ms	1	1	100.00
		chip_sw_kmac_smoketest	3.963m	3.875ms	1	1	100.00
		chip_sw_otbn_smoketest	4.583m	4.698ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	2.783m	3.672ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.345m	3.962ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.805m	5.323ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.743m	3.956ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.557m	4.796ms	1	1	100.00
		chip_sw_uart_smoketest	3.469m	4.183ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	19.603s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	14.714s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	8.333m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.656s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.032m	4.546ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.356m	4.415ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.457m	4.499ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.324m	4.976ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	13.407s		0	1	0.00
		chip_rv_dm_lc_disabled	10.110m	18.318ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	11.842s		0	1	0.00
		chip_sw_lc_walkthrough_prod	11.814s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	15.198s		0	1	0.00
		chip_sw_lc_walkthrough_rma	18.796s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	13.407s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	24.793s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	31.379s		0	1	0.00
		rom_volatile_raw_unlock	10.860s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.786s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	8.116m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	8.191m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.342m	5.147ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.342m	5.147ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	12.610s		0	1	0.00
		chip_same_csr_outstanding	10.720s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	12.610s		0	1	0.00
		chip_same_csr_outstanding	10.720s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	56.410s	52.021us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.760s	12.387us	1	1	100.00
		xbar_smoke_large_delays	4.757m	2.698ms	1	1	100.00
		xbar_smoke_slow_rsp	5.114m	2.027ms	1	1	100.00
		xbar_random_zero_delays	30.440s	30.327us	1	1	100.00
		xbar_random_large_delays	14.989m	8.331ms	1	1	100.00
		xbar_random_slow_rsp	22.622m	8.842ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	46.950s	32.642us	1	1	100.00
		xbar_error_and_unmapped_addr	1.231m	166.208us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.290m	224.094us	1	1	100.00
		xbar_error_and_unmapped_addr	1.231m	166.208us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.339m	140.200us	1	1	100.00
		xbar_access_same_device_slow_rsp	35.489m	14.275ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	32.960s	34.448us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	8.062m	1.442ms	1	1	100.00
		xbar_stress_all_with_error	3.265m	198.330us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	13.241m	590.937us	1	1	100.00
		xbar_stress_all_with_reset_error	1.708m	132.039us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.968s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.427s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.285s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.552s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.939s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.945s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	13.661s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	13.133s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.871s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.112s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.735s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.058s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	13.058s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	13.818s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.387s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.267s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.410s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.161s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.158s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.857s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.207s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.487s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.998s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.455s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.528s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	14.199s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	11.756s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.281s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.125s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.751s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.241s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.749s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	13.077s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.565s		0	1	0.00
		rom_e2e_asm_init_dev	11.700s		0	1	0.00
		rom_e2e_asm_init_prod	11.749s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.088s		0	1	0.00
		rom_e2e_asm_init_rma	11.303s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	13.276s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.805s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.592s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.272s		0	1	0.00
V2		TOTAL			64	205	31.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.297m	4.549ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.318m	3.975ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.184s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.972s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.486s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	13.714s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	16.259m	14.004ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.099m		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	14.839m	12.803ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	13.681s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.594s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.184s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.972s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.486s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.152s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.119s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.595s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.480m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.121m	15.930ms	1	1	100.00
		chip_plic_all_irqs_0	7.977m	7.338ms	1	1	100.00
		chip_plic_all_irqs_10	9.501m	7.718ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.313m	5.202ms	1	1	100.00
		chip_sw_dma_abort	4.574m	3.816ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.220s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.967s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.266s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.500s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.932s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.702s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	12.266s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.359s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.647s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.717s		0	1	0.00
		chip_sw_mbx_smoketest	4.090m	6.149ms	1	1	100.00
		TOTAL			75	247	30.36

Failure Buckets

Job returned non-zero exit code has 141 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.3721808977933746763691214383821967124884040362933504198629181920019432341444
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  DEBUG: /nightly/runs/opentitan/rules/autogen.bzl:452:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (06a03b)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (df0700)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 532.703s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.14918040484139362694366608004068000463890496882617862309093309770041383032991
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (030658)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 519.970s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.57679518189542179744080775776641332059363046978648611507502654800137560014009
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (f20682)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 517.269s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.50850883808164152273673674373106415850216562372514839787014772082124509949916
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (c8011b)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 541.317s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.26993882577241608195760263449782193092565426282240964179835954903155279145907
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (f62ee7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 515.840s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 136 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.55797083304957725400158510228963096901687716842066343298755399128570887847157
    Line 473, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.51504537145160466654189337023700853013165683282196523302741064672420545487950
    Line 409, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.96423686135736271705748531058945534259159531692787423575380126755459825612803
    Line 406, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.74902948619490574444212656873202588751179549325424874757766260384897275030177
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.65572977483597339065064132984472254504190977580576265085080803940466652381812
    Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_rstmgr_alert_info has 1 failures.

0.chip_sw_rstmgr_alert_info.30206401499868838774744204995351919968844471437753849080952517633354147614840
Line 521, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30017.280031 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30017.280031 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.62499598477475550718216066521647368529885988566905540843339633225809863161784
Line 569, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20016.985020 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20016.985020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.14213153552853949593642924582101072946582094305004432955449955265476093638766
Line 548, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.150271 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.150271 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.70239716230629096671940469756508621837367074310491995786930403720967418629225
Line 548, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18023.659325 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18023.659325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.28457327380324676520938771665665359672036361374423169848134088708344298500790
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.106712926058153136519840616646633552721765842691179801737980821764934318754240
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.14858967911408578783729542978909798995077128793035233169961803245166195434857
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.25426571984378538374888868970015960849663407962167352200595231732037831581536
Line 460, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8020.753290 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (55074285025042047836187604718920939397244332235823284540653786265869728591904 [0x79c2f0cf989237820040fa0ed230ab3be7713d9c801265e0aca514754fc3b020] vs 37652612425945775673912625056310390720284632771609932503027421977016517222485 [0x533e9f97ff67c2d0436902f3db1b213058f70be161727f54059e1f883ccf6055])
  UVM_INFO @ 8020.753290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.75079219018794973000142629821077131130112126258828502868260132432813036060924
Line 459, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 9556.942600 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (39572566790294094229259495278193979731396814892736046267700214503950423443284 [0x577d47715ed78b24b2194fb136e6218dfbfbfd78e69872c1cf3f72e2ac384754] vs 68049949065116121123526627514060324957806274621439161057848621812432777652682 [0x9672e800435055e24bc9b10c6034341d3fc9d9b1e614ff000e2097fb5a8229ca])
  UVM_INFO @ 9556.942600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.82218168636276358977679015882380642915091435776518252662625697075599749576062
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3819.575130 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h8455b6df  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3f  a_opcode: 'h0  a_user: 'h26926  d_param: 'h0  d_source: 'h3f  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3819.575130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.9202995134213886504454370515737403587079350030961326936528188436893737695879
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3421.891926 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'habf7a8d7  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h19  a_opcode: 'h1  a_user: 'h248df  d_param: 'h0  d_source: 'h19  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3421.891926 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.12757159603048206133649141513277618016020743315493112638392701754337721315253
    Line 550, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5043.136792 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5043.136792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_smoketest_sim_dv(sw/device/tests/soc_proxy_smoketest.c:34)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceTwo, kDifToggleEnabled) returns * has 1 failures:
- Test chip_sw_soc_proxy_smoketest has 1 failures.
  - 0.chip_sw_soc_proxy_smoketest.99338939082158614740219790269010890101050657423491999337886390433951365083567
    Line 486, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
```
  UVM_ERROR @ 4673.241558 us: (sw_logger_if.sv:526) [soc_proxy_smoketest_sim_dv(sw/device/tests/soc_proxy_smoketest.c:34)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceTwo, kDifToggleEnabled) returns 3
  UVM_INFO @ 4673.241558 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.61506110533435676271798392087571974517567826340587497473480084754333010473029
    Line 496, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4745.417182 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4745.417182 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.35263628608630694270970945518585520648409401129675340572000634935160339130276
    Line 538, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 3767.021132 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 3767.021132 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.99541849601638754102242614271283016473022567233132580929083121823488750104122
    Line 507, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4771.696640 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4771.696640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.84535876632575551765015406024470913972411060983668644254001189221295053916272
    Line 533, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5189.245216 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5189.245216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.38557935433049976720419504184207685948275837235429432873492807094014000099663
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@36012) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.48814659170833714736290899615343977517321193812910741713067213171233283435988
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 5146.846156 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@36012) { a_addr: 'h1465411  a_data: 'h1af83385  a_mask: 'h0  a_size: 'h0  a_param: 'h0  a_source: 'hea  a_opcode: 'h4  a_user: 'h25d94  d_param: 'h0  d_source: 'hea  d_data: 'h0  d_size: 'h0  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h4aa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5146.846156 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.53419188819177178910756719743853388066885674404559837461945054307430540677829
    Line 402, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14782.614292 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14782.614292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.95015835100402847828110306658013043670687517869476185940987566206447470447587
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.23174970878712093130350467857305471170640659391064794844052684618676726883506
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3815.674828 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3815.674828 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```