DMA Simulation Results

Monday May 05 2025 17:08:26 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	10.000s	417.783us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	4.460ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	345.603us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	58.897us	1	1	100.00
V1	csr_rw	dma_csr_rw	3.000s	20.507us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	14.000s	13.443ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	8.000s	1.457ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	42.755us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	3.000s	20.507us	1	1	100.00
		dma_csr_aliasing	8.000s	1.457ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.067m	45.731ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	3.283m	123.345ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	8.533m	48.801ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	3.917m	95.724ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	3.283m	123.345ms	1	1	100.00
V2	dma_abort	dma_abort	14.000s	1.033ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.767m	7.722ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	22.491us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	434.400us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	434.400us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	58.897us	1	1	100.00
		dma_csr_rw	3.000s	20.507us	1	1	100.00
		dma_csr_aliasing	8.000s	1.457ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	190.093us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	58.897us	1	1	100.00
		dma_csr_rw	3.000s	20.507us	1	1	100.00
		dma_csr_aliasing	8.000s	1.457ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	190.093us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	18.000s	536.753us	1	1	100.00
		dma_generic_stress	3.917m	95.724ms	1	1	100.00
		dma_handshake_stress	3.283m	123.345ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	8.000s	1.173ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	2.000m	7.180ms	1	1	100.00
		dma_longer_transfer	12.000s	576.484us	1	1	100.00
		TOTAL			21	21	100.00