HMAC Simulation Results

Monday May 05 2025 17:08:26 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 3.660s 179.011us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.980s 40.665us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.680s 14.848us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 12.380s 1.094ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.550s 441.138us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.330s 17.938us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.680s 14.848us 1 1 100.00
hmac_csr_aliasing 5.550s 441.138us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 20.780s 5.291ms 1 1 100.00
V2 back_pressure hmac_back_pressure 58.730s 14.063ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.126m 19.551ms 1 1 100.00
hmac_test_sha384_vectors 6.217m 12.970ms 1 1 100.00
hmac_test_sha512_vectors 4.740m 9.600ms 1 1 100.00
hmac_test_hmac256_vectors 10.700s 1.518ms 1 1 100.00
hmac_test_hmac384_vectors 11.410s 1.057ms 1 1 100.00
hmac_test_hmac512_vectors 9.350s 477.696us 1 1 100.00
V2 burst_wr hmac_burst_wr 16.650s 8.192ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 23.165m 14.547ms 1 1 100.00
V2 error hmac_error 1.059m 1.579ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.024m 1.835ms 1 1 100.00
V2 save_and_restore hmac_smoke 3.660s 179.011us 1 1 100.00
hmac_long_msg 20.780s 5.291ms 1 1 100.00
hmac_back_pressure 58.730s 14.063ms 1 1 100.00
hmac_datapath_stress 23.165m 14.547ms 1 1 100.00
hmac_burst_wr 16.650s 8.192ms 1 1 100.00
hmac_stress_all 4.677m 31.353ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 3.660s 179.011us 1 1 100.00
hmac_long_msg 20.780s 5.291ms 1 1 100.00
hmac_back_pressure 58.730s 14.063ms 1 1 100.00
hmac_datapath_stress 23.165m 14.547ms 1 1 100.00
hmac_wipe_secret 1.024m 1.835ms 1 1 100.00
hmac_test_sha256_vectors 3.126m 19.551ms 1 1 100.00
hmac_test_sha384_vectors 6.217m 12.970ms 1 1 100.00
hmac_test_sha512_vectors 4.740m 9.600ms 1 1 100.00
hmac_test_hmac256_vectors 10.700s 1.518ms 1 1 100.00
hmac_test_hmac384_vectors 11.410s 1.057ms 1 1 100.00
hmac_test_hmac512_vectors 9.350s 477.696us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 3.660s 179.011us 1 1 100.00
hmac_long_msg 20.780s 5.291ms 1 1 100.00
hmac_back_pressure 58.730s 14.063ms 1 1 100.00
hmac_datapath_stress 23.165m 14.547ms 1 1 100.00
hmac_burst_wr 16.650s 8.192ms 1 1 100.00
hmac_error 1.059m 1.579ms 1 1 100.00
hmac_wipe_secret 1.024m 1.835ms 1 1 100.00
hmac_test_sha256_vectors 3.126m 19.551ms 1 1 100.00
hmac_test_sha384_vectors 6.217m 12.970ms 1 1 100.00
hmac_test_sha512_vectors 4.740m 9.600ms 1 1 100.00
hmac_test_hmac256_vectors 10.700s 1.518ms 1 1 100.00
hmac_test_hmac384_vectors 11.410s 1.057ms 1 1 100.00
hmac_test_hmac512_vectors 9.350s 477.696us 1 1 100.00
hmac_stress_all 4.677m 31.353ms 1 1 100.00
V2 stress_all hmac_stress_all 4.677m 31.353ms 1 1 100.00
V2 alert_test hmac_alert_test 1.560s 37.222us 1 1 100.00
V2 intr_test hmac_intr_test 1.690s 15.289us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.630s 81.004us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.630s 81.004us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.980s 40.665us 1 1 100.00
hmac_csr_rw 1.680s 14.848us 1 1 100.00
hmac_csr_aliasing 5.550s 441.138us 1 1 100.00
hmac_same_csr_outstanding 1.950s 41.731us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.980s 40.665us 1 1 100.00
hmac_csr_rw 1.680s 14.848us 1 1 100.00
hmac_csr_aliasing 5.550s 441.138us 1 1 100.00
hmac_same_csr_outstanding 1.950s 41.731us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.870s 70.435us 1 1 100.00
hmac_tl_intg_err 4.290s 285.006us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.290s 285.006us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 3.660s 179.011us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.220s 38.830us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 11.828m 66.048ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.480s 291.388us 1 1 100.00
TOTAL 28 28 100.00