I2C Simulation Results

Monday May 05 2025 17:08:26 UTC

GitHub Revision: `1a62881`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	58.950s	7.135ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	17.430s	15.179ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.610s	44.157us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.730s	208.797us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.150s	590.108us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.990s	36.231us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.980s	61.791us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.730s	208.797us	1	1	100.00
		i2c_csr_aliasing	1.990s	36.231us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.940s	859.519us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	7.302m	78.351ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.127m	3.255ms	1	1	100.00
V2	host_override	i2c_host_override	1.640s	38.018us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	52.610s	15.463ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.228m	6.956ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.740s	1.575ms	1	1	100.00
		i2c_host_fifo_fmt_empty	4.020s	1.364ms	1	1	100.00
		i2c_host_fifo_reset_rx	3.620s	170.329us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.030m	7.448ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	27.070s	867.597us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.660s	13.834us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.070s	2.052ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	3.597m	89.023ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.730s	801.743us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	19.650s	5.214ms	1	1	100.00
		i2c_target_intr_smoke	5.760s	1.179ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.020s	406.142us	1	1	100.00
		i2c_target_fifo_reset_tx	1.970s	435.635us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	2.449m	41.157ms	1	1	100.00
		i2c_target_stress_rd	19.650s	5.214ms	1	1	100.00
		i2c_target_intr_stress_wr	2.650m	19.816ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.210s	2.587ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	3.370s	2.718ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.120s	8.961ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.210s	693.503us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.710s	8.535ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.800s	229.254us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.127m	3.255ms	1	1	100.00
		i2c_host_perf_precise	24.770s	2.947ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	27.070s	867.597us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.280s	247.106us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.020s	2.290ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.860s	472.889us	1	1	100.00
		i2c_target_nack_txstretch	2.010s	273.861us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.460s	202.459us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.350s	465.859us	1	1	100.00
V2	alert_test	i2c_alert_test	1.550s	23.322us	1	1	100.00
V2	intr_test	i2c_intr_test	1.590s	34.520us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.560s	1.391ms	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.560s	1.391ms	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.610s	44.157us	1	1	100.00
		i2c_csr_rw	1.730s	208.797us	1	1	100.00
		i2c_csr_aliasing	1.990s	36.231us	1	1	100.00
		i2c_same_csr_outstanding	1.680s	171.066us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.610s	44.157us	1	1	100.00
		i2c_csr_rw	1.730s	208.797us	1	1	100.00
		i2c_csr_aliasing	1.990s	36.231us	1	1	100.00
		i2c_same_csr_outstanding	1.680s	171.066us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.550s	228.681us	1	1	100.00
		i2c_sec_cm	1.850s	162.169us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.550s	228.681us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	26.730s	727.676us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.890s	210.210us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	10.480s	975.355us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 2 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.32171239665812782748673713720204179643115776997654405762403209732259936138018
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 210209609 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 169 [0xa9])
  UVM_INFO @ 210209609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.55443401495018110131036337512768800416590078155524908624728976954411494649861
    Line 102, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 975354560 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 64 [0x40])
  UVM_INFO @ 975354560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.106560640995927566238626178020329077595208487731798378935824769164531362326139
Line 191, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 78351374336 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @9163946

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.49712705752837128408717476819788511410832107192293325503615850617610073198893
    Line 86, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 727675532 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 727675532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.27065215177234633093342597495496938876569177013561564508306581155442721928477
    Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  UVM_ERROR @  13834007 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------
```