KEYMGR Simulation Results

Monday May 05 2025 17:08:26 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.220s	121.200us	1	1	100.00
V1	random	keymgr_random	3.590s	65.702us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.990s	260.030us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.580s	7.523us	0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.400s	257.895us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	3.410s	288.426us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.880s	19.711us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.580s	7.523us	0	1	0.00
		keymgr_csr_aliasing	3.410s	288.426us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	3.310s	176.799us	1	1	100.00
V2	sideload	keymgr_sideload	2.810s	36.788us	1	1	100.00
		keymgr_sideload_kmac	2.790s	122.050us	1	1	100.00
		keymgr_sideload_aes	15.480s	2.889ms	1	1	100.00
		keymgr_sideload_otbn	2.500s	24.994us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.600s	81.913us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.840s	237.204us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.550s	260.034us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.140s	153.028us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.430s	68.365us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.580s	199.966us	1	1	100.00
V2	stress_all	keymgr_stress_all	18.470s	755.226us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.730s	24.335us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.640s	85.859us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.400s	175.683us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.400s	175.683us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.990s	260.030us	1	1	100.00
		keymgr_csr_rw	1.580s	7.523us	0	1	0.00
		keymgr_csr_aliasing	3.410s	288.426us	1	1	100.00
		keymgr_same_csr_outstanding	1.550s	5.363us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.990s	260.030us	1	1	100.00
		keymgr_csr_rw	1.580s	7.523us	0	1	0.00
		keymgr_csr_aliasing	3.410s	288.426us	1	1	100.00
		keymgr_same_csr_outstanding	1.550s	5.363us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	5.750s	248.023us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	5.750s	248.023us	1	1	100.00
		keymgr_tl_intg_err	1.960s	27.736us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.490s	445.608us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.490s	445.608us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.490s	445.608us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.490s	445.608us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	2.330s	33.833us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	5.750s	248.023us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	5.750s	248.023us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.960s	27.736us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.490s	445.608us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.310s	176.799us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.590s	65.702us	1	1	100.00
		keymgr_csr_rw	1.580s	7.523us	0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.590s	65.702us	1	1	100.00
		keymgr_csr_rw	1.580s	7.523us	0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.590s	65.702us	1	1	100.00
		keymgr_csr_rw	1.580s	7.523us	0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.840s	237.204us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.430s	68.365us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.430s	68.365us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.590s	65.702us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.240s	81.218us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	5.750s	248.023us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	5.750s	248.023us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	5.750s	248.023us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	5.900s	215.284us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.840s	237.204us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	5.750s	248.023us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	5.750s	248.023us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	5.750s	248.023us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	5.900s	215.284us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	5.900s	215.284us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	5.750s	248.023us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	5.900s	215.284us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	5.750s	248.023us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	5.900s	215.284us	1	1	100.00
V2S		TOTAL			4	6	66.67
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	4.300s	171.386us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			25	30	83.33

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 4 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.17724155181274366432098552497477805125040408185005580549535757934489926142920
      Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
        UVM_ERROR @  33833215 ps: (keymgr_csr_assert_fpv.sv:411) [ASSERT FAILED] sealing_sw_binding_4_rd_A
        UVM_INFO @  33833215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.50926875483781005614844147365851456417139395695678380521922621257026651611957
      Line 100, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
        UVM_ERROR @  27735519 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_3_rd_A
        UVM_INFO @  27735519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_rw has 1 failures.

    • 0.keymgr_csr_rw.86542387130417125933586371866500806329740263767179788301140823790568138580893
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
        UVM_ERROR @   7523415 ps: (keymgr_csr_assert_fpv.sv:391) [ASSERT FAILED] sealing_sw_binding_0_rd_A
        UVM_INFO @   7523415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.31081416837850325766609671763328939086693291814707349251025923633165610850810
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
        UVM_ERROR @   5362934 ps: (keymgr_csr_assert_fpv.sv:421) [ASSERT FAILED] sealing_sw_binding_6_rd_A
        UVM_INFO @   5362934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.96357251706141654391473279572268967144984145986103021093143583853686002775130
      Line 255, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 171386186 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 171386186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---