KMAC/MASKED Simulation Results

Monday May 05 2025 17:08:26 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	16.640s	1.102ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.700s	15.182us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.810s	19.127us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	11.000s	409.071us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.950s	147.082us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.130s	43.611us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.810s	19.127us	1	1	100.00
		kmac_csr_aliasing	3.950s	147.082us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.720s	36.921us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.990s	307.519us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	22.290m	15.890ms	1	1	100.00
V2	burst_write	kmac_burst_write	18.130m	27.421ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.660s	8.768ms	1	1	100.00
		kmac_test_vectors_sha3_256	28.640s	4.901ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.012m	49.472ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.750s	2.382ms	1	1	100.00
		kmac_test_vectors_shake_128	2.444m	8.146ms	1	1	100.00
		kmac_test_vectors_shake_256	5.407m	24.024ms	1	1	100.00
		kmac_test_vectors_kmac	3.880s	149.250us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.200s	64.718us	1	1	100.00
V2	sideload	kmac_sideload	2.731m	2.830ms	1	1	100.00
V2	app	kmac_app	4.300s	335.932us	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.895m	37.866ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.779m	14.266ms	1	1	100.00
V2	error	kmac_error	1.236m	16.380ms	1	1	100.00
V2	key_error	kmac_key_error	8.720s	1.141ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	6.150s	239.680us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	21.310s	843.665us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.660s	27.660us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	12.260s	1.115ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.410s	40.571us	1	1	100.00
V2	stress_all	kmac_stress_all	14.819m	68.341ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.960s	11.660us	1	1	100.00
V2	alert_test	kmac_alert_test	1.680s	18.491us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.710s	93.520us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.710s	93.520us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.700s	15.182us	1	1	100.00
		kmac_csr_rw	1.810s	19.127us	1	1	100.00
		kmac_csr_aliasing	3.950s	147.082us	1	1	100.00
		kmac_same_csr_outstanding	2.210s	131.092us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.700s	15.182us	1	1	100.00
		kmac_csr_rw	1.810s	19.127us	1	1	100.00
		kmac_csr_aliasing	3.950s	147.082us	1	1	100.00
		kmac_same_csr_outstanding	2.210s	131.092us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.370s	192.063us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.370s	192.063us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.370s	192.063us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.370s	192.063us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.780s	402.224us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	59.650s	18.747ms	1	1	100.00
		kmac_tl_intg_err	1.820s	35.340us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.820s	35.340us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.410s	40.571us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	16.640s	1.102ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.731m	2.830ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.370s	192.063us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	59.650s	18.747ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	59.650s	18.747ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	59.650s	18.747ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	16.640s	1.102ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.410s	40.571us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	59.650s	18.747ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.332m	7.403ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	16.640s	1.102ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.915m	5.709ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.9722651271324091879786507815006845641030280169939346356587697386280250011280
      Line 222, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5709499455 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 5709499455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.10090594942226735752174131985047576507366467839851700143692239499426125197858
      Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
        UVM_ERROR @  35339752 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
        UVM_INFO @  35339752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---