KMAC/UNMASKED Simulation Results

Monday May 05 2025 17:08:26 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	24.710s	2.006ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.660s	28.477us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.710s	27.666us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.830s	8.015ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.590s	1.011ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.110s	35.200us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.710s	27.666us	1	1	100.00
		kmac_csr_aliasing	4.590s	1.011ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.680s	40.677us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.890s	119.252us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	5.413m	18.486ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.809m	24.049ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.010s	11.163ms	1	1	100.00
		kmac_test_vectors_sha3_256	16.741m	16.355ms	1	1	100.00
		kmac_test_vectors_sha3_384	15.330s	5.095ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.470s	1.035ms	1	1	100.00
		kmac_test_vectors_shake_128	2.231m	9.565ms	1	1	100.00
		kmac_test_vectors_shake_256	1.049m	2.012ms	1	1	100.00
		kmac_test_vectors_kmac	2.530s	314.843us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.470s	499.256us	1	1	100.00
V2	sideload	kmac_sideload	3.536m	17.322ms	1	1	100.00
V2	app	kmac_app	1.922m	6.311ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.910m	7.024ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.459m	10.866ms	1	1	100.00
V2	error	kmac_error	2.419m	11.487ms	1	1	100.00
V2	key_error	kmac_key_error	5.850s	2.679ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.940s	351.475us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	19.460s	1.150ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	15.590s	316.623us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	10.000s	1.119ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	10.300s	501.305us	1	1	100.00
V2	stress_all	kmac_stress_all	10.191m	218.958ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.550s	14.189us	1	1	100.00
V2	alert_test	kmac_alert_test	1.500s	29.621us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.590s	150.459us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.590s	150.459us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.660s	28.477us	1	1	100.00
		kmac_csr_rw	1.710s	27.666us	1	1	100.00
		kmac_csr_aliasing	4.590s	1.011ms	1	1	100.00
		kmac_same_csr_outstanding	2.870s	635.569us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.660s	28.477us	1	1	100.00
		kmac_csr_rw	1.710s	27.666us	1	1	100.00
		kmac_csr_aliasing	4.590s	1.011ms	1	1	100.00
		kmac_same_csr_outstanding	2.870s	635.569us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.120s	146.162us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.120s	146.162us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.120s	146.162us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.120s	146.162us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.860s	188.477us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	19.660s	9.296ms	1	1	100.00
		kmac_tl_intg_err	3.780s	726.390us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.780s	726.390us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	10.300s	501.305us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	24.710s	2.006ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.536m	17.322ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.120s	146.162us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	19.660s	9.296ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	19.660s	9.296ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	19.660s	9.296ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	24.710s	2.006ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	10.300s	501.305us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	19.660s	9.296ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.234m	200.000ms	0	1	0.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	24.710s	2.006ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.250s	82.865us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_mubi has 1 failures.

    • 0.kmac_mubi.68259587411527976275043957419718706018244547226149592502791547132592341407983
      Line 250, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_mubi/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.102865353873056684097924403130261472766929933134101685110669205961375150771703
      Line 93, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  82864637 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
        UVM_INFO @  82864637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---