OTBN Simulation Results

Monday May 05 2025 17:08:26 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	48.057us	1	1	100.00
V1	single_binary	otbn_single	10.000s	53.300us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	15.114us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	36.111us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	77.168us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	17.184us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	175.969us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	36.111us	1	1	100.00
		otbn_csr_aliasing	6.000s	17.184us	1	1	100.00
V1	mem_walk	otbn_mem_walk	27.000s	1.253ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	16.000s	707.791us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	28.000s	279.774us	1	1	100.00
V2	multi_error	otbn_multi_err	40.000s	221.969us	1	1	100.00
V2	back_to_back	otbn_multi	28.000s	227.021us	1	1	100.00
V2	stress_all	otbn_stress_all	1.750m	645.854us	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	178.120us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	15.623us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	14.000s	47.422us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	88.970us	1	1	100.00
V2	intr_test	otbn_intr_test	5.000s	111.946us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	8.000s	135.396us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	8.000s	135.396us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	15.114us	1	1	100.00
		otbn_csr_rw	6.000s	36.111us	1	1	100.00
		otbn_csr_aliasing	6.000s	17.184us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	38.248us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	15.114us	1	1	100.00
		otbn_csr_rw	6.000s	36.111us	1	1	100.00
		otbn_csr_aliasing	6.000s	17.184us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	38.248us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	10.000s	53.565us	1	1	100.00
		otbn_dmem_err	10.000s	21.464us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	9.000s	106.522us	1	1	100.00
		otbn_controller_ispr_rdata_err	10.000s	86.886us	1	1	100.00
		otbn_mac_bignum_acc_err	11.000s	73.495us	1	1	100.00
		otbn_urnd_err	10.000s	19.500us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	15.641us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	21.042us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	87.249us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	9.000s	41.360us	0	1	0.00
		otbn_tl_intg_err	24.000s	297.394us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	26.000s	158.373us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	9.000s	41.360us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	9.000s	41.360us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	48.057us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	10.000s	21.464us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	53.565us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	24.000s	297.394us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	178.120us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	53.565us	1	1	100.00
		otbn_dmem_err	10.000s	21.464us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	15.623us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	15.641us	1	1	100.00
		otbn_sec_cm	9.000s	41.360us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	9.000s	41.360us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	10.000s	53.300us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	53.565us	1	1	100.00
		otbn_dmem_err	10.000s	21.464us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	15.623us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	15.641us	1	1	100.00
		otbn_sec_cm	9.000s	41.360us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	9.000s	41.360us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	178.120us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	53.565us	1	1	100.00
		otbn_dmem_err	10.000s	21.464us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	15.623us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	15.641us	1	1	100.00
		otbn_sec_cm	9.000s	41.360us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	9.000s	41.360us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	10.000s	53.300us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	65.110us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	34.823us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	24.000s	91.409us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	24.000s	91.409us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	9.000s	20.511us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	9.000s	41.360us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	9.000s	41.360us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	139.603us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	9.000s	41.360us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	9.000s	41.360us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	45.348us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	45.348us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	10.000s	25.887us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	10.000s	53.300us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	10.000s	53.300us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	10.000s	53.300us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	28.000s	227.021us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	10.000s	53.300us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	10.000s	53.300us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	39.151us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	10.000s	53.300us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	9.000s	41.360us	0	1	0.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	3.533m	1.046ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	41	95.12

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.15911971222022483101993347011374921156485206298282150470000139634584745938096
      Line 107, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 25887086 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  25887086 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  25887086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.69839530287633794901147506198559491456913512379612407747574138244534009402317
      Line 109, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 41360382 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 41360382 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  41360382 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  41360382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---