ROM_CTRL/64KB Simulation Results

Monday May 05 2025 17:08:26 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.770s	305.584us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	7.870s	1.710ms	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.140s	294.941us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.350s	295.799us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.750s	1.034ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.370s	739.054us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.140s	294.941us	1	1	100.00
		rom_ctrl_csr_aliasing	8.750s	1.034ms	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.410s	292.179us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.670s	290.726us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.090s	447.443us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	16.980s	855.937us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	13.850s	2.024ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	8.430s	293.883us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	8.620s	1.168ms	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	8.620s	1.168ms	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	7.870s	1.710ms	1	1	100.00
		rom_ctrl_csr_rw	7.140s	294.941us	1	1	100.00
		rom_ctrl_csr_aliasing	8.750s	1.034ms	1	1	100.00
		rom_ctrl_same_csr_outstanding	8.980s	1.075ms	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	7.870s	1.710ms	1	1	100.00
		rom_ctrl_csr_rw	7.140s	294.941us	1	1	100.00
		rom_ctrl_csr_aliasing	8.750s	1.034ms	1	1	100.00
		rom_ctrl_same_csr_outstanding	8.980s	1.075ms	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	38.110s	13.852ms	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	26.170s	2.107ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.610m	450.199us	1	1	100.00
		rom_ctrl_tl_intg_err	1.116m	1.544ms	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.610m	450.199us	1	1	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	2.610m	450.199us	1	1	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	38.110s	13.852ms	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	38.110s	13.852ms	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	38.110s	13.852ms	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	38.110s	13.852ms	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	38.110s	13.852ms	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.610m	450.199us	1	1	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.610m	450.199us	1	1	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.770s	305.584us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.770s	305.584us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.770s	305.584us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.116m	1.544ms	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	38.110s	13.852ms	0	1	0.00
		rom_ctrl_kmac_err_chk	13.850s	2.024ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	38.110s	13.852ms	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	38.110s	13.852ms	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	38.110s	13.852ms	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	26.170s	2.107ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.610m	450.199us	1	1	100.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	35.530s	2.432ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:695) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.34710658774671699434204302257312881938958366240437131270712968757837205701915
      Line 73, in log /nightly/runs/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 13851807546 ps: (cip_base_vseq.sv:695) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
        UVM_INFO @ 13851807546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---