RV_TIMER Simulation Results

Monday May 05 2025 17:08:26 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.490s	24.914us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.620s	225.583us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.460s	14.158us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.660s	303.410us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.530s	13.304us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.550s	68.814us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.460s	14.158us	1	1	100.00
		rv_timer_csr_aliasing	1.530s	13.304us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.520s	1.018ms	1	1	100.00
V2	disabled	rv_timer_disabled	4.300s	1.761ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	2.369m	148.955ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	2.369m	148.955ms	1	1	100.00
V2	stress	rv_timer_stress_all	3.030s	4.596ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.570s	20.433us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.600s	43.693us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.890s	51.975us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.890s	51.975us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.620s	225.583us	1	1	100.00
		rv_timer_csr_rw	1.460s	14.158us	1	1	100.00
		rv_timer_csr_aliasing	1.530s	13.304us	1	1	100.00
		rv_timer_same_csr_outstanding	1.540s	25.491us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.620s	225.583us	1	1	100.00
		rv_timer_csr_rw	1.460s	14.158us	1	1	100.00
		rv_timer_csr_aliasing	1.530s	13.304us	1	1	100.00
		rv_timer_same_csr_outstanding	1.540s	25.491us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.910s	125.549us	1	1	100.00
		rv_timer_tl_intg_err	1.730s	169.093us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.730s	169.093us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	34.580s	9.991ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.500s	33.575us	1	1	100.00
		rv_timer_max	1.470s	36.957us	1	1	100.00
		TOTAL			19	19	100.00