SPI_HOST Simulation Results

Monday May 05 2025 17:08:26 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	19.000s	5.583ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	23.963us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	22.566us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	116.020us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	26.765us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	61.108us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	22.566us	1	1	100.00
		spi_host_csr_aliasing	4.000s	26.765us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	56.607us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	27.323us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	25.183us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	52.835us	1	1	100.00
		spi_host_error_cmd	4.000s	55.771us	1	1	100.00
		spi_host_event	13.000s	6.509ms	1	1	100.00
V2	clock_rate	spi_host_speed	7.000s	233.704us	1	1	100.00
V2	speed	spi_host_speed	7.000s	233.704us	1	1	100.00
V2	chip_select_timing	spi_host_speed	7.000s	233.704us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	24.000s	878.144us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	30.254us	1	1	100.00
V2	cpol_cpha	spi_host_speed	7.000s	233.704us	1	1	100.00
V2	full_cycle	spi_host_speed	7.000s	233.704us	1	1	100.00
V2	duplex	spi_host_smoke	19.000s	5.583ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	19.000s	5.583ms	1	1	100.00
V2	stress_all	spi_host_stress_all	14.000s	543.477us	1	1	100.00
V2	spien	spi_host_spien	13.000s	2.436ms	1	1	100.00
V2	stall	spi_host_status_stall	1.100m	4.191ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	19.000s	4.503ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	52.835us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	24.447us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	24.338us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	136.433us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	136.433us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	23.963us	1	1	100.00
		spi_host_csr_rw	4.000s	22.566us	1	1	100.00
		spi_host_csr_aliasing	4.000s	26.765us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	35.291us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	23.963us	1	1	100.00
		spi_host_csr_rw	4.000s	22.566us	1	1	100.00
		spi_host_csr_aliasing	4.000s	26.765us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	35.291us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	103.137us	1	1	100.00
		spi_host_sec_cm	4.000s	311.619us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	103.137us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	3.883m	26.562ms	1	1	100.00
		TOTAL			26	26	100.00