SRAM_CTRL/MAIN Simulation Results

Monday May 05 2025 17:08:26 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.033m	2.154ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.580s	49.732us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.610s	27.185us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.440s	68.136us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.680s	44.242us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.210s	1.778ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.610s	27.185us	1	1	100.00
		sram_ctrl_csr_aliasing	1.680s	44.242us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.050m	16.426ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	54.060s	2.621ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	11.864m	60.656ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.757m	22.648ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	23.937m	120.919ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.037m	7.579ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	46.980s	52.876ms	1	1	100.00
V2	executable	sram_ctrl_executable	2.058m	3.735ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	14.420s	16.151ms	1	1	100.00
		sram_ctrl_partial_access_b2b	2.450m	8.580ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	42.040s	3.014ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	8.390s	2.763ms	1	1	100.00
		sram_ctrl_throughput_w_readback	9.810s	772.642us	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.393m	8.105ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.700s	1.405ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.274h	931.378ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.520s	30.451us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.770s	287.859us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.770s	287.859us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.580s	49.732us	1	1	100.00
		sram_ctrl_csr_rw	1.610s	27.185us	1	1	100.00
		sram_ctrl_csr_aliasing	1.680s	44.242us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.620s	33.904us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.580s	49.732us	1	1	100.00
		sram_ctrl_csr_rw	1.610s	27.185us	1	1	100.00
		sram_ctrl_csr_aliasing	1.680s	44.242us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.620s	33.904us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	16.770s	3.848ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.510s	13.808us	0	1	0.00
		sram_ctrl_tl_intg_err	2.740s	451.077us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.510s	13.808us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.740s	451.077us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.393m	8.105ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.393m	8.105ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.610s	27.185us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	2.058m	3.735ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	2.058m	3.735ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	2.058m	3.735ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	46.980s	52.876ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.740s	709.788us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	16.770s	3.848ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.900s	3.544ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.033m	2.154ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.033m	2.154ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	2.058m	3.735ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.510s	13.808us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	46.980s	52.876ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.510s	13.808us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.510s	13.808us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.033m	2.154ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.510s	13.808us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.096m	13.882ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.79571197518455899933563218688194632497489798035977643879375890809184634959666
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  13808465 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  13808465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---