SRAM_CTRL/RET Simulation Results

Monday May 05 2025 17:08:26 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	19.330s	649.015us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.420s	32.263us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.630s	26.519us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.960s	27.024us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.680s	14.930us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.820s	105.068us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.630s	26.519us	1	1	100.00
		sram_ctrl_csr_aliasing	1.680s	14.930us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.390s	663.848us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.240s	361.008us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.747m	10.809ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.619m	13.815ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	38.830s	4.298ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	12.406m	3.239ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.520s	2.087ms	1	1	100.00
V2	executable	sram_ctrl_executable	6.144m	4.105ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	52.010s	204.528us	1	1	100.00
		sram_ctrl_partial_access_b2b	2.157m	6.753ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.880s	54.954us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	4.880s	99.904us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.043m	932.823us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.472m	15.321ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.890s	39.869us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	3.905m	6.523ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.980s	18.707us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.240s	163.951us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.240s	163.951us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.420s	32.263us	1	1	100.00
		sram_ctrl_csr_rw	1.630s	26.519us	1	1	100.00
		sram_ctrl_csr_aliasing	1.680s	14.930us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.860s	25.695us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.420s	32.263us	1	1	100.00
		sram_ctrl_csr_rw	1.630s	26.519us	1	1	100.00
		sram_ctrl_csr_aliasing	1.680s	14.930us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.860s	25.695us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.460s	1.631ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.580s	4.358us	0	1	0.00
		sram_ctrl_tl_intg_err	2.210s	156.827us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.580s	4.358us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.210s	156.827us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.472m	15.321ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.472m	15.321ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.630s	26.519us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.144m	4.105ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.144m	4.105ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.144m	4.105ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.520s	2.087ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.860s	85.423us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.460s	1.631ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.150s	35.864us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	19.330s	649.015us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	19.330s	649.015us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.144m	4.105ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.580s	4.358us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.520s	2.087ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.580s	4.358us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.580s	4.358us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	19.330s	649.015us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.580s	4.358us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.473m	3.990ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.80217868487494518299119890080981901937225282198756858415293526240954500721700
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   4358062 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   4358062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---