UART Simulation Results

Monday May 05 2025 17:08:26 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.650s	304.329us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.550s	32.085us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.530s	16.648us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.160s	417.717us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.690s	29.748us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.530s	76.485us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.530s	16.648us	1	1	100.00
		uart_csr_aliasing	1.690s	29.748us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	5.350s	13.868ms	1	1	100.00
V2	parity	uart_smoke	1.650s	304.329us	1	1	100.00
		uart_tx_rx	5.350s	13.868ms	1	1	100.00
V2	parity_error	uart_intr	4.431m	245.226ms	1	1	100.00
		uart_rx_parity_err	33.260s	124.607ms	1	1	100.00
V2	watermark	uart_tx_rx	5.350s	13.868ms	1	1	100.00
		uart_intr	4.431m	245.226ms	1	1	100.00
V2	fifo_full	uart_fifo_full	36.650s	135.641ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	42.570s	42.501ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	36.060s	35.685ms	1	1	100.00
V2	rx_frame_err	uart_intr	4.431m	245.226ms	1	1	100.00
V2	rx_break_err	uart_intr	4.431m	245.226ms	1	1	100.00
V2	rx_timeout	uart_intr	4.431m	245.226ms	1	1	100.00
V2	perf	uart_perf	9.350m	16.099ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.570s	2.123ms	1	1	100.00
V2	line_loopback	uart_loopback	2.570s	2.123ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	25.240s	44.485ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.530s	3.468ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.520s	643.902us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	7.160s	3.443ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.413m	97.104ms	1	1	100.00
V2	stress_all	uart_stress_all	6.600m	309.392ms	1	1	100.00
V2	alert_test	uart_alert_test	1.300s	11.632us	1	1	100.00
V2	intr_test	uart_intr_test	1.450s	27.638us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.990s	24.182us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.990s	24.182us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.550s	32.085us	1	1	100.00
		uart_csr_rw	1.530s	16.648us	1	1	100.00
		uart_csr_aliasing	1.690s	29.748us	1	1	100.00
		uart_same_csr_outstanding	1.570s	25.227us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.550s	32.085us	1	1	100.00
		uart_csr_rw	1.530s	16.648us	1	1	100.00
		uart_csr_aliasing	1.690s	29.748us	1	1	100.00
		uart_same_csr_outstanding	1.570s	25.227us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.710s	585.726us	1	1	100.00
		uart_tl_intg_err	1.960s	84.737us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.960s	84.737us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	11.570s	1.304ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00