CHIP Simulation Results

Monday May 05 2025 17:08:26 UTC

GitHub Revision: `1a62881`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.152m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.152m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	2.247m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.625m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.577m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.886m	5.474ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.886m	5.474ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.886m	5.474ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	38.970s	10.200us	0	1	0.00
		chip_sw_example_manufacturer	31.015s		0	1	0.00
		chip_sw_example_concurrency	4.191m	4.000ms	1	1	100.00
		chip_sw_uart_smoketest_signed	13.064s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.610s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.140s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.140s		0	1	0.00
V1	xbar_smoke	xbar_smoke	9.530s	12.855us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.168m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.205m	8.417ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.509m	5.923ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.063m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	44.976s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.516m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.234m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.640s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.640s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.352m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.176m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	16.356s		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	16.356s		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.913m	5.295ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.843m	4.587ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.205m	13.599ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.599s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.528s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	16.154m	20.689ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.742m	6.470ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	18.691m	18.022ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	18.691m	18.022ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.419s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.208m	4.736ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.208m	4.736ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.078m	18.016ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.557m	4.951ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.310m	5.266ms	1	1	100.00
		chip_sw_aes_idle	4.401m	4.834ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.536m	3.936ms	1	1	100.00
		chip_sw_kmac_idle	4.238m	4.913ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.024s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	13.125s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.824s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	10.749s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.228s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.587s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.378s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.281s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.278s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.620s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.255s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.228s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.587s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.378s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.281s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.278s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.620s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.255s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.901s		0	1	0.00
		chip_sw_aes_enc_jitter_en	56.720s	10.360us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	49.440s	10.220us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.990s	10.340us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.990s	10.140us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.025s		0	1	0.00
		chip_sw_clkmgr_jitter	4.476m	5.089ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.752m	3.916ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	16.211s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	52.590s	10.260us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	47.690s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	50.710s	10.340us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	1.046m	10.240us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	52.180s	10.100us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.447s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.475s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.281s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	10.568s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	17.351m	11.970ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.769m	13.524ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.208m	4.736ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.465s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.769m	13.524ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	17.494s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	11.593s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.647s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	20.663s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	23.316s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	17.351m	11.970ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.205m	13.599ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	23.460m	20.022ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.087m	9.096ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.819m	30.018ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.125m	3.591ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	17.351m	11.970ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.533s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.999s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	17.351m	11.970ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	13.101s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.819m	30.018ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	14.234s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	13.075s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.822s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.714s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.524s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	13.791s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.999s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.324s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.070s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.324s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.324s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.324s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	5.990m	7.086ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	26.085s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	20.661s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	11.773s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	25.103s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.324s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.527m	7.646ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.293m	13.371ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.990s		0	1	0.00
		chip_prim_tl_access	2.012m	4.230ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.228s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.587s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.378s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.281s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.278s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.620s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.255s		0	1	0.00
		chip_rv_dm_lc_disabled	16.154m	20.689ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.972m	5.759ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	56.720s	10.360us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.527m	4.214ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.401m	4.834ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.890m	5.554ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	49.440s	10.220us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.536m	3.936ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.594m	5.340ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.248m	4.175ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	49.990s	10.140us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.527m	7.646ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.324s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	39.750s	10.400us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.181m	4.520ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.238m	4.913ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.602s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.602s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.063s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.800m	5.874ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.440s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.527m	7.646ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.990s	10.340us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	11.146s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.901s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.310m	5.266ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.310m	5.266ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.310m	5.266ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.187m	6.038ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.293m	13.371ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.293m	13.371ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.473m	6.751ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.025s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.990s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	17.351m	11.970ms	1	1	100.00
		chip_sw_data_integrity_escalation	16.356s		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.324s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.187m	6.038ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.527m	7.646ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.473m	6.751ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.380m	3.702ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.187m	6.038ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.527m	7.646ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.473m	6.751ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.380m	3.702ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.324s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.867s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.070s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	26.085s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	20.661s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	11.773s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	25.103s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.324s		0	1	0.00
		chip_prim_tl_access	2.012m	4.230ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.012m	4.230ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	19.355s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	19.488s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.475s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.901s		0	1	0.00
		chip_sw_aes_enc_jitter_en	56.720s	10.360us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	49.440s	10.220us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.990s	10.340us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.990s	10.140us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.025s		0	1	0.00
		chip_sw_clkmgr_jitter	4.476m	5.089ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	4.526m	4.500ms	0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	4.526m	4.500ms	0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.575m	5.360ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.049m	4.324ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.623m	5.061ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.228m	6.901ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.469m	3.919ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.341m	4.303ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.380m	3.702ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	23.460m	20.022ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	23.460m	20.022ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.864m	4.647ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.401m	5.195ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.352m	3.559ms	1	1	100.00
		chip_sw_csrng_smoketest	3.397m	3.556ms	1	1	100.00
		chip_sw_gpio_smoketest	4.234m	5.608ms	1	1	100.00
		chip_sw_hmac_smoketest	3.460m	4.543ms	1	1	100.00
		chip_sw_kmac_smoketest	4.255m	5.833ms	1	1	100.00
		chip_sw_otbn_smoketest	4.343m	5.652ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.147m	2.952ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.594m	5.295ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.561m	4.191ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.973m	5.284ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.424m	4.234ms	1	1	100.00
		chip_sw_uart_smoketest	3.229m	5.767ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.682s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	13.064s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.168m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	11.599s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.877m	3.515ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.997m	5.850ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.339m	3.555ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.903m	3.992ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	19.517s		0	1	0.00
		chip_rv_dm_lc_disabled	16.154m	20.689ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	21.073s		0	1	0.00
		chip_sw_lc_walkthrough_prod	13.881s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	24.043s		0	1	0.00
		chip_sw_lc_walkthrough_rma	25.684s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	19.517s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.429s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	22.980s		0	1	0.00
		rom_volatile_raw_unlock	10.652s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.271s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.977m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.930m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.803m	5.329ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.803m	5.329ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.140s		0	1	0.00
		chip_same_csr_outstanding	14.990s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.140s		0	1	0.00
		chip_same_csr_outstanding	14.990s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	59.650s	153.408us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.060s	12.352us	1	1	100.00
		xbar_smoke_large_delays	4.131m	2.167ms	1	1	100.00
		xbar_smoke_slow_rsp	6.063m	2.295ms	1	1	100.00
		xbar_random_zero_delays	33.920s	31.032us	1	1	100.00
		xbar_random_large_delays	17.709m	8.916ms	1	1	100.00
		xbar_random_slow_rsp	32.557m	12.729ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	27.350s	50.453us	1	1	100.00
		xbar_error_and_unmapped_addr	1.444m	190.782us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	2.292m	399.289us	1	1	100.00
		xbar_error_and_unmapped_addr	1.444m	190.782us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.068m	131.911us	1	1	100.00
		xbar_access_same_device_slow_rsp	31.560m	12.381ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	31.610s	27.124us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	7.605m	433.568us	1	1	100.00
		xbar_stress_all_with_error	4.431m	885.863us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	20.099m	1.624ms	1	1	100.00
		xbar_stress_all_with_reset_error	6.138m	196.641us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.705s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	13.085s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	15.255s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	14.055s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	16.029s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.892s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.711s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.923s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	13.530s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.067s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	13.580s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	14.329s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.318s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.071s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.197s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.969s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.861s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.682s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13.664s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.934s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.187s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.328s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.539s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.844s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.735s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.813s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	13.449s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.228s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.506s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.262s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.553s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.994s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.766s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.268s		0	1	0.00
		rom_e2e_asm_init_dev	12.615s		0	1	0.00
		rom_e2e_asm_init_prod	11.096s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.766s		0	1	0.00
		rom_e2e_asm_init_rma	11.227s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.905s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.368s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.444s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.981s		0	1	0.00
V2		TOTAL			64	205	31.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.441m	5.769ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.115m	4.376ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.808s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.611s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.910s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	13.577s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	17.351m	11.970ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	12.505s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	16.716m	13.912ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	15.146s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.962s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.808s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.611s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.910s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.837s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.727s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.654s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.307m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	17.910m	12.748ms	1	1	100.00
		chip_plic_all_irqs_0	9.019m	6.758ms	1	1	100.00
		chip_plic_all_irqs_10	9.077m	6.793ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.514m	4.151ms	1	1	100.00
		chip_sw_dma_abort	4.021m	4.171ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.576s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.606s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.656s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.781s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.575s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.491s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.865s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.000s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.704s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.355s		0	1	0.00
		chip_sw_mbx_smoketest	4.139m	3.637ms	1	1	100.00
		TOTAL			75	247	30.36

Failure Buckets

Job returned non-zero exit code has 140 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.33151674109781721877347700340423254002096832126282587257305147507476290661896
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (ed6732)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 15.319s, Critical Path: 0.04s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.22805630109554347582423629215598946733999066416086138757838819889980915858900
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (5383f4)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 5.673s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.106493226575886609170647799990511696479781929329763847629266659848541575422528
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (4a2480)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 130.282s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.8291335381762118855637922641453190124184107616814180239021013412239565311069
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (e55737)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 119.793s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.100214630478573120839360592729450077163197922858953325001366611585205346838736
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (09937d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 118.715s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 135 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.87154234525809240250849466829852469714542590967093614994227034026172039718697
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.62522513134023238162348157995759610598314566077680314228610797596479289242022
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.80284388378527555951713355244778444283794654023048219610865669946972420971227
    Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.14493096981741142737799125740431339315240959503487449790577795933620687162544
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.76963859318200656847202921856711857854965509276083803460718340172204570825877
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_rstmgr_alert_info has 1 failures.

0.chip_sw_rstmgr_alert_info.24276389586438104349770351084580377086985807205807463567474684144767071391484
Line 466, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30017.774015 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30017.774015 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.86762964542154902855772895409069936980017529469611078628770171818952643689504
Line 450, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20022.443237 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20022.443237 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.79582340241410851225019953306824512978293832435017817710796537550099337066610
Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18021.602479 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18021.602479 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.8481885916610541177586688852658787769564343751388193732721119669161794449707
Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18016.247099 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.247099 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.100734309715951590876331156637088322974548731905805826252219420002100444638711
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.107650749652200911293784848674853390723668572453961152512399829555160232735483
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.7435442519817686497522966732242854376233201528392671295800153940099913424642
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.47538374109803309337353618991421658628557058013280282942099831294859079846878
Line 478, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 7646.169676 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (103902893216926251837361113266774411484402990043074637451734945950330654173816 [0xe5b6f419f1c4fd80364182871c56591181b6fd478555575ab3fecc8aeb662a78] vs 91869596377035685166040925081673931703781788453450487376980326798552569445727 [0xcb1c594f6dc0562e9f5c780be4130248f29a772c838d0872053ebea173d37d5f])
  UVM_INFO @ 7646.169676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.6156961697057209164243763657249896966120407991507711044247640371282512795880
Line 480, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7085.546300 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (101084502072397615400701054236699671066346578056461294310697752874446337103277 [0xdf7bccf842d92c223c8ea6bfd8617edabab94b61a2eda1f001af3f16f16855ad] vs 63397968843291134396061663906634591946548497077668538067175810197198006185405 [0x8c29fa8fbf0a3a57aaffa3bdb695610851e1d878e1234e75e41c1d18c468edbd])
  UVM_INFO @ 7085.546300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.14834683577180886033659667080780543408511646082595166123517051327253699131533
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 5295.031291 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hae6f53d8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1d  a_opcode: 'h1  a_user: 'h248e5  d_param: 'h0  d_source: 'h1d  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5295.031291 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.46734799849057592761371698548881435940751461458879781428010528861447978927327
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4587.428813 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h62f60084  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h0  a_user: 'h2690f  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4587.428813 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.103356770447937612349878978959655452494156225537602325377352971348697439482186
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.45574044110791629478698824728090584925603296466949414570155296707513786360273
    Line 454, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5922.529880 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5922.529880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_smoketest_sim_dv(sw/device/tests/soc_proxy_smoketest.c:34)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceTwo, kDifToggleEnabled) returns * has 1 failures:
- Test chip_sw_soc_proxy_smoketest has 1 failures.
  - 0.chip_sw_soc_proxy_smoketest.105386882428041279853289070003553068970125413029776574526526781864445362615385
    Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
```
  UVM_ERROR @ 4499.884328 us: (sw_logger_if.sv:526) [soc_proxy_smoketest_sim_dv(sw/device/tests/soc_proxy_smoketest.c:34)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceTwo, kDifToggleEnabled) returns 3
  UVM_INFO @ 4499.884328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.67147736819753813598470263445644363577923023728437400141529995837192781916374
    Line 449, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5360.131712 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5360.131712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.86561705431719944846934777224358831635454924394262360973479023650820862766902
    Line 453, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4324.481440 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4324.481440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.23017705129435866532609652457651691998122940536118858510926733027639901374095
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4736.222776 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4736.222776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.82733123382602944311743910110177913730892031375698166174693008705435110138137
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6901.452436 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6901.452436 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.14895590580975592256420027027078155174240504131773372534854863385593733426825
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.109289839304711595547894478699895266522554161993723352343662080289898295207389
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 5329.325340 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 5329.325340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.66486457931690884398100710328095985772655917454614493322886380169722386681405
    Line 402, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13599.297600 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13599.297600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.53543585526764974314524674004481885199043863986854923844824795328002443346396
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.63472678626013032383910206577631463177246449886176506739740907723275951269073
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4171.104112 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4171.104112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```