DMA Simulation Results

Tuesday May 06 2025 17:03:32 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	299.789us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	365.779us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	2.572ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	111.928us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	19.161us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	12.000s	1.214ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	288.502us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	29.034us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	19.161us	1	1	100.00
		dma_csr_aliasing	6.000s	288.502us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.883m	59.281ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	23.633m	124.178ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	57.450m	1.556s	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	4.050m	346.726ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	23.633m	124.178ms	1	1	100.00
V2	dma_abort	dma_abort	14.000s	3.800ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	2.033m	10.346ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	37.023us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	27.478us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	27.478us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	111.928us	1	1	100.00
		dma_csr_rw	4.000s	19.161us	1	1	100.00
		dma_csr_aliasing	6.000s	288.502us	1	1	100.00
		dma_same_csr_outstanding	5.000s	92.965us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	111.928us	1	1	100.00
		dma_csr_rw	4.000s	19.161us	1	1	100.00
		dma_csr_aliasing	6.000s	288.502us	1	1	100.00
		dma_same_csr_outstanding	5.000s	92.965us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	31.000s	101.919us	1	1	100.00
		dma_generic_stress	4.050m	346.726ms	1	1	100.00
		dma_handshake_stress	23.633m	124.178ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	968.415us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.767m	12.880ms	1	1	100.00
		dma_longer_transfer	19.000s	978.721us	1	1	100.00
		TOTAL			21	21	100.00